R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1431

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin
Power-
Down
Mode
Module
standby
mode
Transition
Conditions
Set the MSTP
bits in
STBCR2 to
STBCR6 to 1
2. RTC operates when the START bit in the RCR2 register is set to 1. For details, see
3. Setting the bits RAMKP3 to RAMKP0 in the RAMKP register to 1 enables to retain the
4. Deep standby mode can be canceled by an interrupt (NMI or IRQ) or a reset (manual
5. The stored contents are initialized when software standby mode is canceled by a
6. The stored contents can be retained even when software standby mode is canceled by
States.
section 14, Realtime Clock (RTC). When deep standby mode is canceled by a power-
on reset, the running state cannot be retained. Make the initial setting for the realtime
clock again.
data in the corresponding area on the on-chip RAM during the transition to deep
standby. However, the stored contents are initialized when deep standby mode is
canceled by a power-on reset.
reset or power-on reset). However, when deep standby mode is canceled by the NMI
interrupt or IRQ interrupt, power-on reset exception handling is executed instead of
interrupt exception handling. The power-on reset exception handling is executed also in
the cancellation of deep standby mode by manual reset.
power-on reset.
a power-on reset by disabling access to the on-chip RAM (high-speed) by means of the
RAME bits in the SYSCR1 register or the RAMWE bits in the SYSCR2 register.
CPG
Running Running Held
CPU
CPU
Register
On-Chip
RAM
(High-
Speed)
Cash
Memory
Running Running
On-Chip
RAM
(for Data
Retention)
State*
1
On-Chip
Peripheral
Modules
Specified
module
halted
Rev. 3.00 Sep. 28, 2009 Page 1399 of 1650
RTC
Halted
Section 28 Power-Down Modes
Power
supply
Running Auto-
External
Memory
refresh
REJ09B0313-0300
Canceling
Procedure
• Clear MSTP bit to
• Power-on reset
0
(only for H-UDI,
UBC and DMAC)