R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 156

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 5 Exception Handling
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
Rev. 3.00 Sep. 28, 2009 Page 124 of 1650
REJ09B0313-0300
Type
Interrupt
Instruction Trap instruction (TRAPA instruction)
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BRAF.
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Exception Handling
On-chip peripheral modules I
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction*
instructions in FPU module standby state), instructions that rewrite the PC*
32-bit instructions*
instruction)
3
1
, RESBANK instruction, DIVS instruction, and DIVU
(including FPU instructions and FPU-related CPU
Serial communications interface with FIFO
(SCIF)
Synchronous serial communications unit
(SSU)
Serial sound interface (SSI)
AND/NAND flash memory controller (FLCTL)
Realtime clock (RTC)
Controller area network (RCAN-TL1)
2
C bus interface 3 (IIC3)
2
,
Priority
High
Low