R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 529

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

11.3.9
TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count
reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request
will be issued.
TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Initial value:
11.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4
TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or
trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and
TADCORB_4, respectively.
TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Initial value:
Note:
Note:
R/W:
R/W:
Bit:
Bit:
TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
R/W
R/W
Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and
TADCORB_4)
and TADCOBRB_4)
15
15
1
1
R/W
R/W
14
14
1
1
R/W
R/W
13
13
1
1
R/W
R/W
12
12
1
1
R/W
R/W
11
11
1
1
R/W
R/W
10
10
1
1
R/W
R/W
9
1
9
1
R/W
R/W
8
1
8
1
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
R/W
7
1
7
1
Rev. 3.00 Sep. 28, 2009 Page 497 of 1650
R/W
R/W
6
1
6
1
R/W
R/W
5
1
5
1
R/W
R/W
4
1
4
1
R/W
R/W
3
1
3
1
REJ09B0313-0300
R/W
R/W
2
1
2
1
R/W
R/W
1
1
1
1
R/W
R/W
0
1
0
1