R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 598

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which

the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set.

The settings should be made so as to achieve the following relationship between these two

The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and

TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and

TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode

The updated PWM cycle is reflected from the next cycle when the data update is performed at the

crest, and from the current cycle when performed in the trough. Figure 11.42 illustrates the

operation when the PWM cycle is updated at the crest.

See the following section, Register Data Updating, for the method of updating the data in each

buffer register.

Rev. 3.00 Sep. 28, 2009 Page 566 of 1650

REJ09B0313-0300

PWM Cycle Setting

Counter value TGRC_3

With dead time: TGRA_3 set value = TCDR set value + TDDR set value

Without dead time: TGRA_3 set value = TCDR set value + 1

Figure 11.42 Example of PWM Cycle Updating