R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 123

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(1)
In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset.
(2)
The exception handling state is a transient state that occurs when exception handling sources such
as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception handling vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception handling vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
(3)
In the program execution state, the CPU sequentially executes the program.
(4)
In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP
instruction places the CPU in sleep mode, software standby mode, or deep standby mode.
(5)
In the bus-released state, the CPU releases bus to a device that has requested it.
Reset State
Exception Handling State
Program Execution State
Power-Down State
Bus-Released State
Rev. 3.00 Sep. 28, 2009 Page 91 of 1650
REJ09B0313-0300
Section 2 CPU