R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 966

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 19 Controller Area Network (RCAN-TL1)
• TTW[1:0] (Time Trigger Window): These bits show the attribute of time windows. Please
The first 16-bit area specifies the time that triggers the transmission of the message in cycle time.
The second 16-bit area specifies the basic cycle in the system matrix where the transmission must
start (Offset) and the frequency for periodic transmission. When the internal TTT register matches
to the CYCTR value, and the internal Offset matches to CCR value transmission is attempted from
the corresponding Mailbox. In order to enable this function, the CMAX (Cycle Maximum
Register) must be set to a value different from 3'b111, the Timer (TCNTR) must be running
(TTCR0 bit15 = 1), the corresponding MBC must be set to 3'b000 and the corresponding TXPR
bit must be set. Once TXPR is set by S/W, RCAN-TL1 does not clear the corresponding TXPR bit
(among Mailbox-30 to 24) to carry on performing the periodic transmission. In order to stop the
periodic transmission, TXPR must be cleared by TXCR. Please note that in this case it is possible
that both TXACK and ABACK are set for the same Mailbox if TXACK is not cleared right after
completion of transmission. Please refer to figure 19.7.
Rev. 3.00 Sep. 28, 2009 Page 934 of 1650
REJ09B0313-0300
TTW[1]
0
0
1
1
note that once a merged arbitrating window is opened by TTW = 2'b10, the window must be
closed by TTW = 2'b11. Several messages with TTW = 2'b10 may be used within the start and
the end of a merged arbitrating window.
MB29 to 24
MB30
H'114 + N*32
H'116 + N*32
H'114 + N*32
TTW[0]
0
1
0
1
15
15
TTW[1:0]
14
14
13
13
12
12
Figure 19.6 Tx-Trigger control field
Offset[5:0]
11
11
Description
Exclusive window (initial value)
Arbitrating window
Start of merged arbitrating window
End of merged arbitrating window
10
10
Tx-Trigger Time (Cycle Time)
Tx-Trigger Time (Cycle Time)
9
9
8
8
7
0
7
6
6
0
5
0
5
4
4
0
3
0
3
2
2
rep_factor[2:0]
1
1
0
0
Word
Word
Word
Trigger Time
Trigger Time
TT control