R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1003

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bits 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively.
(7)
The MBIMR1 and MBIMR0 are 16-bit read/write registers. The MBIMR only prevents the setting
of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt, IRR[2]
– Remote Frame Receive Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] – Message
OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the corresponding
bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and IRR[9]) but
does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR. Similarly
when a mailbox has been configured for transmission, a mask prevents the generation of an
Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or
abortion of transmission (IRR[8]), however, it does not prevent the RCAN-TL1 from clearing the
corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does
not prevent the RCAN-TL1 from clearing the corresponding TXPR/TXCR bit + setting the
ABACK bit for abortion of the transmission.
A mask is set by writing a ‘1’ to the corresponding bit position for the mailbox activity to be
masked. At reset all mailbox interrupts are masked.
• MBIMR1
Bits 15 to 0 — Enable or disable interrupt requests from individual Mailbox-31 to Mailbox-16
respectively.
Bit[15:0]: RFPR0
0
1
Initial value:
Mailbox Interrupt Mask Register (MBIMR)
R/W:
Bit:
R/W
15
1
R/W
14
1
Description
[Clearing Condition] Writing ‘1’ (Initial value)
Corresponding Mailbox received Remote Frame
[Setting Condition]
Completion of remote frame receive in corresponding mailbox
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
MBIMR1[15:0]
R/W
8
1
Section 19 Controller Area Network (RCAN-TL1)
R/W
7
1
Rev. 3.00 Sep. 28, 2009 Page 971 of 1650
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
REJ09B0313-0300
2
1
R/W
1
1
R/W
0
1