R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 195

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

6.3.9
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow
exception. IBNR also indicates the bank number to which saving is performed next through the
bits BN3 to BN0.
Initial value:
Bit
15, 14
13
12 to 4
R/W:
Bit:
Bank Number Register (IBNR)
R/W
Bit Name
BE[1:0]
BOVE
⎯
15
0
BE[1:0]
R/W
14
0
BOVE
R/W
13
0
Initial
Value
All 0
00
0
12
R
0
-
11
R
0
-
R/W
R/W
R/W
R
10
R
0
-
Description
Register Bank Enable
These bits enable or disable use of register banks.
00: Use of register banks is disabled for all interrupts.
01: Use of register banks is enabled for all interrupts
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the setting of
Register Bank Overflow Enable
Enables of disables register bank overflow exception.
0: Generation of register bank overflow exception is
1: Generation of register bank overflow exception is
Reserved
These bits are always read as 0. The write value should
always be 0.
R
9
0
disabled
enabled
-
The setting of IBCR is ignored.
except NMI and user break. The setting of IBCR is
ignored.
IBCR.
R
8
0
-
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 163 of 1650
R
6
0
-
Section 6 Interrupt Controller (INTC)
R
5
0
-
R
4
0
-
R
3
0
REJ09B0313-0300
R
2
0
BN[3:0]
R
1
0
R
0
0