R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 271

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

The bus state controller (BSC) outputs control signals for various types of memory and external
devices that are connected to the external address space. BSC functions enable this LSI to connect
directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1
1. External address space
2. Normal space interface
3. Burst ROM interface (clocked asynchronous)
4. MPX-I/O interface
5. SDRAM interface
⎯ A maximum of 64 Mbytes for each of areas CS0 to CS7.
⎯ Can specify the normal space interface, SRAM interface with byte selection, burst ROM
⎯ Can select the data bus width (8, 16, or 32 bits) for each address space.
⎯ Controls insertion of wait cycles for each address space.
⎯ Controls insertion of wait cycles for each read access and write access.
⎯ Can set independent idle cycles during the continuous access for five cases: read-write (in
⎯ Supports the interface that can directly connect to the SRAM.
⎯ High-speed access to the ROM that has the page mode function.
⎯ Can directly connect to a peripheral LSI that needs an address/data multiplexing.
⎯ Can set the SDRAM in up to two areas.
⎯ Multiplex output for row address/column address.
⎯ Efficient access by single read/single write.
⎯ High-speed access in bank-active mode.
⎯ Supports an auto-refresh and self-refresh.
⎯ Supports low-frequency and power-down modes.
⎯ Issues MRS and EMRS commands.
(clocked synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM, and
PCMCIA interface for each address space.
same space/different spaces), read-read (in same space/different spaces), the first cycle is a
write access.
Features
Section 9 Bus State Controller (BSC)
Rev. 3.00 Sep. 28, 2009 Page 239 of 1650
Section 9 Bus State Controller (BSC)
REJ09B0313-0300