R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1669

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Item
31.4.1 Clock Timing
Figure 31.5 Power-On
Oscillation Settling Time
31.4.2 Control Signal
Timing
Table 31.7 Control
Signal Timing
Figure 31.12 Bus
Release Timing
Page
1533
1534
1536
1538
Revision (See Manual for Details)
Table amended
Figure amended
Table amended
Figure amended
Internal clock
CKIO clock output frequency
CKIO clock output cycle time
CKIO clock output low pulse width
CKIO clock output high pulse width
RES pulse width
TRST pulse width
NMI pulse width
IRQ pulse width
PINT pulse width
BACK setup time when bus buffer off
CKIO
(HIZCNT = 0)
CKIO
(HIZCNT = 1)
RD, RD/WR,
RASU/L,
CASU/L,
CSn, WEn,
BS, CKE
CE2A, CE2B,
FRAME
Item
Item
BREQ
BACK
A25 to A0,
D31 to D0
Note: Oscillation settling time when the internal oscillator is used.
MRES ,
TRST
CKIO,
RES ,
Vcc
t
BREQH
Exit from standby mode
or change the
multiplication ratio of the
PLL circuit
Other than above
TRST pulse width
Exit from standby mode
Other than above
Exit from standby mode
Other than above
t
BREQS
Vcc Min.
Rev. 3.00 Sep. 28, 2009 Page 1637 of 1650
t
t
BACKD
t
BOFF1
BACKS
t
BOFF2
Symbol
t
t
t
t
t
t
t
RESW
TRSW
NMIW
IRQW
PINTW
BACKS
BOFF2
t
OSC1
Symbol
f
t
t
t
OP
cyc
CKOL
CKOH
10
20
20
10
20
10
20
20
0
Min.
t
BREQH
Bφ = 66.66 MHz
40.00
15
t
t
Min.
cyc
cyc
t
BREQS
/2 - t
/2 - t
CKOr
CKOf
Max.
—
—
—
—
—
—
—
—
—
Oscillation settling time
t
BON2
t
t
REJ09B0313-0300
BACKD
BON2
Max.
66.66
25
—
—
Unit Figure
ms
t
t
ms
t
ms
t
t
ns
cyc
cyc
cyc
cyc
cyc
t
BON1
Unit
MHz
ns
ns
ns
Figure 31.9
Figure 31.10
Figure
When
HZCNT = 0
When
HZCNT = 1
Figure
31.4