R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 823

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

This LSI has two synchronous serial communication unit (SSU) channels. The SSU has master
mode in which this LSI outputs clocks as a master device for synchronous serial communication
and slave mode in which clocks are input from an external device for synchronous serial
communication. Synchronous serial communication can be performed with devices having
different clock polarity and clock phase.
16.1
• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source
• Five interrupt sources
• Module standby mode can be set
Section 16 Synchronous Serial Communication Unit (SSU)
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
Transmit end, transmit data register empty, receive data full, overrun error, and conflict error.
The direct memory access controller (DMAC) can be activated by a transmit data register
empty request or a receive data full request to transfer data.
To reduce power consumption, the operation of the SSU can be suspended by stopping the
clock supply to the SSU.
Features
Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Sep. 28, 2009 Page 791 of 1650
REJ09B0313-0300