R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 457

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(3)
In this mode, the transfer is performed in response to the DMA transfer request signal from an on-
chip peripheral module.
Table 10.8 lists the DMA transfer request signals sent from on-chip peripheral modules to DMAC.
If DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0),
AE = 0, and NMIF = 0) in on-chip peripheral module request mode, DMA transfer is started by a
transfer request signal.
In on-chip peripheral module request mode, there are cases where transfer source or destination is
fixed. For details, see table 10.8.
Table 10.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR
RS[3:0] MID
1001
1010
1000
On-Chip Peripheral Module Request
Any
Any
000000 11
000001 11
001000 11
001001 11
001010 11
001011 11
DMARS
RID
Any RCAN-TL10
Any RCAN-TL11
DMA Transfer
Request
Source
reception
reception
USB
USB
SSI_0
SSI_1
SSI_2
SSI_3
DMA Transfer Request Signal
DM0 (reception end)
DM0 (reception end)
USB_DMA0
(receive FIFO full)
USB_DMA0
(transmit FIFO empty)
USB_DMA1
(reception FIFO full)
USB_DMA1
(transmission FIFO empty)
DMA0 (transmission mode)
DMA0 (reception mode)
DMA1 (transmission mode)
DMA1 (reception mode)
DMA2 (transmission mode)
DMA2 (reception mode)
DMA3 (transmission mode)
DMA3 (reception mode)
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 425 of 1650
Transfer
Source
RCAN0
MB0
RCAN1
MB0
D0FIFO
Any
D1FIFO
Any
Any
SSIRDR0
Any
SSIRDR1
Any
SSIRDR2
Any
SSIRDR3
Transfer
Destination
Any
Any
Any
D0FIFO
Any
D1FIFO
SSITDR0
Any
SSITDR1
Any
SSITDR2
Any
SSITDR3
Any
REJ09B0313-0300
Bus
Mode
Cycle
steal
Cycle
steal or
burst
Cycle
steal