R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1041

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

19.4.4
The diagram below shows the message receive sequence.
CAN Bus
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the
RCAN-TL1
Loop (N = 31; N
•Store Message by Overwriting
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
(if IMR1 (IMR2) = 0)
(if MBC is config to receive)
Store Mailbox-Number[N]
and go back to idle state
Valid CAN-ID Received
ID Matched?
Mailbox[N] + LAFM[N]
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared
Interrupt signal
Compare ID with
message has not been updated. TimeStamp may also be updated, however it can be read properly before clearing RXPR[N]/RFPR[N].
and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/
UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Message Receive Sequence
Yes
Yes
≥
0; N = N - 1)
No
End Of Arbitration Field
N = 0?
•Reject Message
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
•Set RXPR[N] (RFPR[N]) *
(if IMR9 = 0)
N = N - 1
No
Interrupt signal
OverWrite
Figure 19.24 Message receive sequence
Yes
IDLE
CPU received interrupt due to CAN Message Reception
OverRun
1
Valid CAN Frame Received
Already Set?
OverWrite or
(RFPR[N])
End Of Frame
OverRun?
RXPR[N]
•Store Message
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(NMC)
(if IMR1 (IMR2) = 0)
MSG
Yes
Interrupt signal
Section 19 Controller Area Network (RCAN-TL1)
No
Rev. 3.00 Sep. 28, 2009 Page 1009 of 1650
Write 1 to RXPR[N]
Read RXPR[N] = 1
Read Mailbox[N]
Check and clear
UMSR[N]
Read IRR
IRR[1]
set?
Yes
Exit Interrupt Service
*
2
Routine
No
REJ09B0313-0300
Write 1 to RFPR[N]
Read RFPR[N] = 1
Read Mailbox[N]
Check and clear
UMSR[N]
*
2