R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
To our customers,
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
On April 1
st
, 2010, NEC Electronics Corporation merged with Renesas Technology
Renesas Electronics website:
Old Company Name in Catalogs and Other Documents
http://www.renesas.com
April 1
Renesas Electronics Corporation
st
, 2010

Related parts for R0K572030S000BE

R0K572030S000BE Summary of contents

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7203 Group 32 Hardware Manual Renesas 32-Bit ...

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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...

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This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be ...

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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...

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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...

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All trademarks and registered trademarks are the property of their respective owners. Rev. 3.00 Sep. 28, 2009 Page viii of xxx REJ09B0313-0300 ...

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Section 1 Overview................................................................................................1 1.1 SH7203 Features.................................................................................................................... 1 1.2 Product Lineup....................................................................................................................... 9 1.3 Block Diagram ..................................................................................................................... 10 1.4 Pin Arrangement .................................................................................................................. 11 1.5 Pin Functions ....................................................................................................................... 12 1.6 Pin Assignments................................................................................................................... 22 Section 2 CPU......................................................................................................47 2.1 Register Configuration......................................................................................................... 47 2.1.1 General Registers ...

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Section 3 Floating-Point Unit (FPU)................................................................... 93 3.1 Features................................................................................................................................ 93 3.2 Data Formats........................................................................................................................ 94 3.2.1 Floating-Point Format............................................................................................. 94 3.2.2 Non-Numbers (NaN) .............................................................................................. 97 3.2.3 Denormalized Numbers .......................................................................................... 98 3.3 Register Descriptions ........................................................................................................... 99 3.3.1 Floating-Point Registers ......................................................................................... 99 3.3.2 Floating-Point Status/Control ...

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Resets ................................................................................................................................. 129 5.2.1 Input/Output Pins.................................................................................................. 129 5.2.2 Types of Reset ...................................................................................................... 129 5.2.3 Power-On Reset .................................................................................................... 130 5.2.4 Manual Reset ........................................................................................................ 132 5.3 Address Errors ................................................................................................................... 133 5.3.1 Address Error Sources .......................................................................................... 133 5.3.2 Address Error Exception Handling ...

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PINT Interrupt Request Register (PIRR) .............................................................. 161 6.3.8 Bank Control Register (IBCR).............................................................................. 162 6.3.9 Bank Number Register (IBNR) ............................................................................ 163 6.4 Interrupt Sources................................................................................................................ 165 6.4.1 NMI Interrupt........................................................................................................ 165 6.4.2 User Break Interrupt ............................................................................................. 165 6.4.3 H-UDI Interrupt .................................................................................................... 165 ...

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Operation ........................................................................................................................... 210 7.4.1 Flow of the User Break Operation ........................................................................ 210 7.4.2 Break on Instruction Fetch Cycle.......................................................................... 211 7.4.3 Break on Data Access Cycle................................................................................. 212 7.4.4 Value of Saved Program Counter ......................................................................... 213 7.4.5 Usage Examples.................................................................................................... 214 7.5 ...

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Refresh Time Constant Register (RTCOR) .......................................................... 296 9.5 Operation ........................................................................................................................... 297 9.5.1 Endian/Access Size and Data Alignment.............................................................. 297 9.5.2 Normal Space Interface ........................................................................................ 304 9.5.3 Access Wait Control ............................................................................................. 309 CSn Assert Period Expansion ............................................................................... 311 9.5.4 9.5.5 MPX-I/O ...

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Setting of the Half-End Flag and Generation of the Half-End Interrupt............. 444 10.5.2 Timing of DACK and TEND Outputs ................................................................ 444 10.5.3 Notice about using external request mode .......................................................... 445 10.5.4 Notice about using on-chip peripheral module request mode ...

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Timer Dead Time Enable Register (TDER)........................................................ 520 11.3.29 Timer Waveform Control Register (TWCR) ...................................................... 521 11.3.30 Bus Master Interface........................................................................................... 522 11.4 Operation ........................................................................................................................... 523 11.4.1 Basic Functions................................................................................................... 523 11.4.2 Synchronous Operation....................................................................................... 529 11.4.3 Buffer Operation................................................................................................. 531 11.4.4 Cascaded Operation ...

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Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode........................................................................ 628 11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode......................................................................................................... 629 11.7.21 Interrupts in Module Standby Mode ................................................................... 629 11.7.22 Simultaneous Capture of ...

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Notes on Register Access ................................................................................... 682 13.4 WDT Usage ....................................................................................................................... 684 13.4.1 Canceling Software Standby Mode..................................................................... 684 13.4.2 Changing the Frequency ..................................................................................... 684 13.4.3 Using Watchdog Timer Mode ............................................................................ 685 13.4.4 Using Interval Timer Mode ................................................................................ 687 13.5 Usage ...

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Usage Notes ....................................................................................................................... 718 14.5.1 Register Writing during RTC Count................................................................... 718 14.5.2 Use of Real-time Clock (RTC) Periodic Interrupts............................................. 718 14.5.3 Transition to Standby Mode after Setting Register ............................................. 718 14.5.4 Notes on Register Read and Write Operations.................................................... 719 ...

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Register Descriptions ......................................................................................................... 794 16.3.1 SS Control Register H (SSCRH) .......................................................................... 795 16.3.2 SS Control Register L (SSCRL) ........................................................................... 797 16.3.3 SS Mode Register (SSMR) ................................................................................... 798 16.3.4 SS Enable Register (SSER) .................................................................................. 799 16.3.5 SS Status Register (SSSR) ...

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I C Bus Format...................................................................................................... 852 17.4.2 Master Transmit Operation ................................................................................... 853 17.4.3 Master Receive Operation..................................................................................... 855 17.4.4 Slave Transmit Operation ..................................................................................... 857 17.4.5 Slave Receive Operation....................................................................................... 860 17.4.6 Clocked Synchronous Serial Format..................................................................... 861 17.4.7 Noise Filter ........................................................................................................... 865 ...

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Audience............................................................................................................... 913 19.1.4 References............................................................................................................. 913 19.1.5 Features................................................................................................................. 914 19.2 Architecture ....................................................................................................................... 915 19.3 Programming Model - Overview ....................................................................................... 919 19.3.1 Memory Map ........................................................................................................ 919 19.3.2 Mailbox Structure ................................................................................................. 921 19.3.3 RCAN-TL1 Control Registers .............................................................................. 938 19.3.4 RCAN-TL1 Mailbox Registers............................................................................. ...

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Setting Analog Input Voltage ........................................................................... 1041 20.7.3 Notes on Board Design ..................................................................................... 1041 20.7.4 Processing of Analog Input Pins....................................................................... 1042 20.7.5 Permissible Signal Source Impedance .............................................................. 1043 20.7.6 Influences on Absolute Precision...................................................................... 1044 20.7.7 A/D Conversion in Deep Standby ...

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Operating Modes ................................................................................................ 1083 22.4.3 Register Setting Procedure.................................................................................. 1084 22.4.4 Command Access Mode ..................................................................................... 1085 22.4.5 Sector Access Mode............................................................................................ 1090 22.4.6 ECC Error Correction ......................................................................................... 1092 22.4.7 Status Read ......................................................................................................... 1093 22.5 Interrupt Sources.............................................................................................................. 1095 22.6 DMA Transfer Specifications ...

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USB Request Length Register (USBLENG) .................................................... 1152 23.3.28 DCP Configuration Register (DCPCFG) .......................................................... 1153 23.3.29 DCP Maximum Packet Size Register (DCPMAXP)......................................... 1155 23.3.30 DCP Control Register (DCPCTR) .................................................................... 1156 23.3.31 Pipe Window Select Register (PIPESEL)......................................................... 1158 23.3.32 Pipe Configuration ...

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LCDC Horizontal Character Number Register (LDHCNR) ............................. 1251 24.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ..................................... 1252 24.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ......................... 1253 24.3.13 LCDC Vertical Total Line Number Register (LDVTLNR).............................. 1254 24.3.14 LCDC Vertical ...

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Port F Control Registers (PFCRH1 to PFCRH4, PFCRL1 to PFCRL4) .................................................. 1346 25.2.11 IRQOUT Function Control Register (IFCR) .................................................... 1360 25.2.12 SSI Oversampling Clock Selection Register (SCSR) ....................................... 1361 25.3 Switching Pin Function ...

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Section 28 Power-Down Modes ......................................................................1397 28.1 Features............................................................................................................................ 1397 28.1.1 Power-Down Modes ......................................................................................... 1397 28.2 Register Descriptions ....................................................................................................... 1400 28.2.1 Standby Control Register (STBCR).................................................................. 1401 28.2.2 Standby Control Register 2 (STBCR2)............................................................. 1402 28.2.3 Standby Control Register 3 (STBCR3)............................................................. 1403 28.2.4 Standby ...

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H-UDI Interrupt ................................................................................................ 1443 29.5 Usage Notes ..................................................................................................................... 1444 Section 30 List of Registers .............................................................................1445 30.1 Register Addresses (by functional module, in order of the corresponding section numbers).......................... 1446 30.2 Register Bits..................................................................................................................... 1469 30.3 Register States in Each Operating ...

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C. Package Dimensions ........................................................................................................ 1615 Main Revisions for this Edition......................................................................... 1617 Index .......................................................................................................1641 Rev. 3.00 Sep. 28, 2009 Page xxx of xxx REJ09B0313-0300 ...

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SH7203 Features This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. The CPU in this LSI is the ...

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Section 1 Overview Table 1.1 SH7203 Features Items Specification • CPU Renesas Technology original SuperH architecture • Compatible with SH-1, SH-2, and SH-2E at object code level • 32-bit internal data bus • Support of an abundant register-set ⎯ Sixteen ...

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Items Specification • Floating-point unit Floating-point co-processor included (FPU) • Supports single-precision (32-bit) and double-precision (64-bit) • Supports data type and exceptions that conforms to IEEE754 standard • Two rounding modes: Round to nearest and round to zero • Two ...

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Section 1 Overview Items Specification • Bus state controller Address space divided into eight areas (0 to 7), each a maximum of 64 (BSC) Mbytes • The following features settable for each area independently ⎯ Bus size (8, 16, or ...

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Items Specification • Power-down modes Four power-down modes provided to reduce the power consumption in this LSI ⎯ Sleep mode ⎯ Software standby mode ⎯ Deep standby mode ⎯ Module standby mode • Multi-function timer Maximum 16 lines of pulse ...

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Section 1 Overview Items Specification • Serial communication Four channels interface with FIFO • Clocked synchronous or asynchronous mode selectable (SCIF) • Simultaneous transmission and reception (full-duplex communication) supported • Dedicated baud rate generator • Separate 16-byte FIFO registers for ...

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Items Specification • Direct-connected memory interface with AND-/NAND-type flash AND/NAND flash memory memory controller • (FLCTL) Read/write in sectors • Two types of transfer modes: Command access mode and sector access mode (512-byte data + 16-byte management code: with ECC) ...

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Section 1 Overview Items Specification • 64-Kbyte memory for high-speed operation (16 Kbytes × 4) On-chip RAM • 16-Kbyte memory for data retention (4 Kbytes × 4) Power supply voltage • Vcc: 1.1 to 1.3 V • PVcc: 3.0 to ...

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Product Lineup Table 1.2 Product Lineup Product Classification Product Code SH7203 R5S72030W200FP Section 1 Overview Package QFP3232-240Cu Rev. 3.00 Sep. 28, 2009 Page 9 of 1650 REJ09B0313-0300 ...

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Section 1 Overview 1.3 Block Diagram SH-2A Floating-point CPU core unit (FPU) Instruction Operand Cache cache memory cache memory controller 8 Kbytes 8 Kbytes Internal LCD bus (IL bus) LCD Bus state LCD I/F I/O controller controller (LCDC) (BSC) Port ...

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Pin Arrangement PB2/SCL1/PINT2/IRQ2 181 PB3/SDA1/PINT3/IRQ3 182 PVcc 183 PVcc 184 PB4/SCL2/PINT4/IRQ4 185 PB5/SDA2/PINT5/IRQ5 186 PVss 187 Vss 188 PB6/SCL3/PINT6/IRQ6 189 PB7/SDA3/PINT7/IRQ7 190 Vcc 191 PD15/D31/PINT7/ADTRG/TIOC4D 192 PD14/D30/PINT6/TIOC4C 193 PD13/D29/PINT5/TEND1/TIOC4B 194 PD12/D28/PINT4/DACK1/TIOC4A 195 PVss 196 PD11/D27/PINT3/DREQ1/TIOC3D 197 PVcc 198 PD10/D26/PINT2/TEND0/TIOC3C ...

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Section 1 Overview 1.5 Pin Functions Table 1.3 Pin Functions Classification Symbol Power supply Vcc Vss PVcc PVss PLLVcc PLLVss Clock EXTAL XTAL CKIO Rev. 3.00 Sep. 28, 2009 Page 12 of 1650 REJ09B0313-0300 I/O Name Function I Power supply ...

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Classification Symbol Operating mode MD control MD_CLK1, MD_CLK0 ASEMD RES System control MRES WDTOVF BREQ BACK I/O Name Function I Mode set Sets the operating mode. Do not change the signal level on this pin during operation. I Clock mode ...

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Section 1 Overview Classification Symbol Interrupts NMI IRQ7 to IRQ0 PINT7 to PINT0 I IRQOUT Address bus A25 to A0 Data bus D31 to D0 CS7 to CS0 Bus control RD RD/ FRAME WAIT WE0 Rev. 3.00 Sep. ...

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Classification Symbol WE1 Bus control WE2 WE3 DQMLL DQMLU DQMUL DQMUU RASU, RASL CASU, CASL CKE CE1A, CE1B CE2A, CE2B ICIOWR ICIORD WE IOIS16 REFOUT I/O Name Function O Byte select Indicates a write access to bits ...

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Section 1 Overview Classification Symbol Direct memory DREQ3 to access controller DREQ0 (DMAC) DACK3 to DACK0 TEND1, TEND0 O Multi-function TCLKA, timer pulse unit TCLKB, 2 (MTU2) TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3B, TIOC3C, ...

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Classification Symbol Realtime clock RTC_X1 (RTC) RTC_X2 Serial TxD3 to TxD0 communication RxD3 to RxD0 interface with SCK3 to SCK0 FIFO (SCIF) RTS3 CTS3 Synchronous SSO1, SSO0 serial SSI1, SSI0 communication SSCK1, SSCK0 I/O unit (SSU) SCS1, SCS0 2 I ...

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Section 1 Overview Classification Symbol Controller area CTx0, CTx1 network (RCAN-TL1) CRx0, CRx1 AND/NAND FOE flash memory controller (FLCTL) FSC FCE FCDE FRB FWE NAF7 to NAF0 Rev. 3.00 Sep. 28, 2009 Page 18 of 1650 REJ09B0313-0300 I/O Name Function ...

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Classification Symbol USB2.0 DP host/function DM module (USB) VBUS REFRIN USB_X1 USB_X2 USBAPVcc USBAPVss USBDPVcc USBDPVss USBAVcc USBAVss USBDVcc USBDVss I/O Name Function I/O USB D+ data USB bus D+ data. I/O USB D– data USB bus D– data. I ...

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Section 1 Overview Classification Symbol LCD controller LCD_DATA15 to (LCDC) LCD_DATA0 LCD_CL1 LCD_CL2 LCD_CLK LCD_FLM LCD_DON LCD_VCPWC LCD_VEPWC LCD_M_DISP A/D converter AN7 to AN0 (ADC) ADTRG D/A converter DA1, DA0 (DAC) Common to AVcc analog-related items AVss AVref Rev. 3.00 ...

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Classification Symbol I/O ports PB11 to PB8, PC14 to PC0, PD15 to PD0, PE15 to PE0, PF30 to PF0 PA7 to PA0, PB7 to PB0 PB12 User debugging TCK interface (H-UDI) TMS TDI TDO TRST Emulator AUDATA3 to interface AUDATA0 ...

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Section 1 Overview 1.6 Pin Assignments Table 1.4 Pin Assignments Function 1 Pin No. Symbol I/O 1 PC10 I/O 2 PC9 I/O 3 PC8 I/O 4 Vcc 5 PC7 I/O 6 Vss 7 PVss 8 PC6 I/O 9 PVcc 10 ...

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Function 1 Pin No. Symbol I/O 13 PC4 I/O 14 PC3 I/O 15 PC2 I/O 16 Vcc 17 PC0 I/O 18 Vss 19 PVss 20 PC1 I/O 21 PVcc ...

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Section 1 Overview Function 1 Pin No. Symbol I PVcc PVss 32 Vss 33 A10 O 34 Vcc 35 A11 O 36 A12 O 37 A13 O 38 A14 ...

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Function 1 Pin No. Symbol I/O 41 PVss 42 A17 O 43 PVcc 44 A18 O 45 A19 O 46 A20 O 47 PE2 I(s)/O 48 PE3 I(s)/O 49 PE0 I(s)/O 50 CKIO I/O 51 Vcc 52 Vss 53 PVss ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 55 XTAL O 56 EXTAL I 57 NMI I(s) 58 PLLVss RES 59 I(s) 60 PLLVcc ASEMD 61 I(s) 62 PE8 I(s)/O 63 PE1 I(s)/O 64 PE4 I(s)/O 65 PVss 66 ...

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Function 1 Pin No. Symbol I/O 69 PE7 I(s)/O 70 PE9 I(s)/O 71 PE10 I(s)/O 72 PE11 I(s)/O 73 PE12 I(s)/O 74 Vcc 75 PC14 I/O 76 Vss 77 PVss 78 RTC_X1 I 79 RTC_X2 O 80 PVcc 81 PE13 ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 83 PE15 I(s)/O 84 PVss 85 PB8 I/O 86 PB9 I/O 87 PB10 I/O 88 PB11 I/O 89 Vcc 90 MD I(s) 91 Vss 92 PVss 93 USB_X1 I 94 USB_X2 ...

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Function 1 Pin No. Symbol I/O 97 MD_CLK0 I(s) 98 USBDPVss 99 USBDPVcc 100 DM I/O 101 DP I/O 102 VBUS I 103 USBAVcc 104 USBAVss 105 REFRIN I 106 USBAPVss 107 USBAPVcc 108 USBDVcc 109 USBDVss 110 PA0 I ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 111 PA1 I 112 PA2 I 113 PA3 I 114 AVcc 115 PA4 I 116 AVref 117 PA5 I 118 PA6 I 119 PA7 I 120 AVss 121 PVss 122 PB12 ...

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Function 1 Pin No. Symbol I/O 125 PF28 I/O 126 PF27 I/O 127 Vcc 128 PF30 I/O 129 Vss 130 PVss 131 AUDIO_X1 I 132 AUDIO_X2 O 133 PVcc 134 PF26 I/O 135 PF25 I/O 136 PF24 I/O 137 PF18 ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 139 PF20 I/O 140 PF21 I/O 141 Vcc 142 PF22 I/O 143 Vss 144 PVss 145 PF23 I/O 146 PVcc 147 PF17 I/O 148 PF16 I/O 149 PF15 I/O 150 PF14 ...

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Function 1 Pin No. Symbol I/O 153 PF11 I/O 154 Vcc 155 PF10 I/O 156 Vss 157 PVss 158 PF9 I/O 159 PVcc 160 PF8 I/O 161 PF7 I(s)/O 162 PF6 I(s)/O 163 PF5 I(s)/O 164 PF4 I(s)/O 165 PF3 ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 167 PF1 I(s)/O 168 Vcc 169 PF0 I(s)/O 170 Vss 171 PVss 172 TMS I 173 PVcc 174 TDI I 175 ASEBRKAK/ASEBRK I(s)/O 176 TRST I(s) 177 TDO O 178 TCK ...

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Function 1 Pin No. Symbol I/O 181 PB2 I(s) 182 PB3 I(s) 183 PVcc 184 PVcc 185 PB4 I(s) 186 PB5 I(s) 187 PVss 188 Vss 189 PB6 I(s) 190 PB7 I(s) 191 Vcc 192 PD15 I/O 193 PD14 I/O ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 195 PD12 I/O 196 PVss 197 PD11 I/O 198 PVcc 199 PD10 I/O 200 PD9 I/O 201 PD8 I/O 202 PD7 I/O 203 PD6 I/O 204 Vcc 205 PD5 I/O 206 ...

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Function 1 Pin No. Symbol I/O 209 PVcc 210 PD3 I/O 211 PD2 I/O 212 PD1 I/O 213 PD0 I/O 214 D15 I/O 215 D14 I/O 216 PVss 217 D13 I/O 218 PVcc 219 D12 I/O 220 D11 I/O 221 ...

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Section 1 Overview Function 1 Pin No. Symbol I/O 223 D8 I/O 224 Vcc 225 D7 I/O 226 Vss 227 PVss 228 D6 I/O 229 PVcc 230 D5 I/O 231 D4 I/O 232 D3 I/O 233 D2 I/O 234 D1 ...

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Function 1 Pin No. Symbol I/O 237 PVcc 238 PC13 I/O 239 PC12 I/O 240 PC11 I/O Function 4 Pin No. Symbol I/O Symbol 237 ⎯ ⎯ ⎯ 238 ⎯ ⎯ ⎯ 239 ⎯ 240 AUDATA1 O [Legend] (s): Schmitt ...

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Section 1 Overview Figure 1.3 (3) Simplified Circuit Diagram (TTL AND Input Buffer with Pull-Up) A/D analog input enable A/D analog input data TTL input data TTL input enable Figure 1.3 (4) Simplified Circuit Diagram (TTL OR Input and A/D ...

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D/A analog output enable D/A analog output data A/D analog input enable A/D analog input data TTL input data TTL input enable Figure 1.3 (5) Simplified Circuit Diagram (TTL OR Input and A/D Input Buffer and D/A Output) latch enable ...

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Section 1 Overview weak keeper enable latch enable output enable output data Figure 1.3 (7) Simplified Circuit Diagram (Output Buffer with Enable, latch enable output enable output data TTL input data TTL input enable Figure 1.3 (8) Simplified Circuit Diagram ...

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TTL input data TTL input enable Figure 1.3 (9) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, with Latch and Weak Keeper) Rev. 3.00 Sep. 28, 2009 Page 43 of 1650 ...

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Section 1 Overview weak keeper enable latch enable output enable output data Schmitt input data Schmitt input enable Figure 1.3 (10) Simplified Circuit Diagram (Bidirectional Buffer, Schmitt AND Input, Rev. 3.00 Sep. 28, 2009 Page 44 of 1650 REJ09B0313-0300 with ...

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TTL input data TTL input enable Schmitt input data Schmitt input enable Figure 1.3 (11) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, Schmitt AND Input, with Latch and Weak Keeper) ...

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Section 1 Overview XOUT (XTAL, AUDIO_X2, USB_X2) XIN (EXTAL, AUDIO_X1, USB_X1) Figure 1.3 (13) Simplified Circuit Diagram (Oscillation Buffer 1) XOUT (RTC_X2) XIN (RTC_X1) Figure 1.3 (14) Simplified Circuit Diagram (Oscillation Buffer 2) Rev. 3.00 Sep. 28, 2009 Page 46 ...

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Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. ...

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Section 2 CPU 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction ...

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Bit Bit Name Initial Value — All — All — — I[3:0] 1111 3, 2 — All 0 1 ...

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Section 2 CPU 2.1.3 System Registers The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results ...

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Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents ...

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Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits word (16 bits changed into a longword ...

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Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, ...

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Section 2 CPU 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions ...

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Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. ...

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Section 2 CPU Table 2.4 T Bit SH-2A CPU Description T bit is set when R0 ≥ R1. CMP/GE R1,R0 The program branches to TRGET0 BT TRGET0 when R0 ≥ R1 and to TRGET1 BF TRGET1 when R0 < R1. ...

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Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of ...

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Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Register direct Rn Register indirect @Rn Register indirect @Rn+ with post- increment Register indirect ...

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Addressing Instruction Mode Format Register indirect @(disp:4, with Rn) displacement Register indirect @(disp:12, with Rn) displacement Indexed register @(R0,Rn) indirect GBR indirect @(disp:8, with GBR) displacement Effective Address Calculation The effective address is the sum of Rn and a 4-bit ...

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Section 2 CPU Addressing Instruction Mode Format Indexed GBR @(R0, GBR) The effective address is the sum of GBR value indirect TBR duplicate @@ indirect with (disp:8, displacement TBR) PC indirect with @(disp:8, displacement PC) Rev. 3.00 Sep. 28, 2009 ...

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Addressing Instruction Mode Format PC relative disp:8 disp:12 Rn Effective Address Calculation The effective address is the sum of PC value and the value that is obtained by doubling the sign- extended 8-bit displacement (disp). PC disp PC + disp ...

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Section 2 CPU Addressing Instruction Mode Format Immediate #imm:20 #imm:8 #imm:8 #imm:8 #imm:3 Rev. 3.00 Sep. 28, 2009 Page 62 of 1650 REJ09B0313-0300 Effective Address Calculation The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended ...

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Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source ...

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Section 2 CPU Instruction Formats m format 15 0 xxxx mmmm xxxx xxxx nm format 15 0 xxxx nnnn mmmm xxxx md format 15 0 xxxx xxxx dddd mmmm Rev. 3.00 Sep. 28, 2009 Page 64 of 1650 REJ09B0313-0300 Source ...

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Instruction Formats nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx nnnn mmmm dddd nmd12 format 32 16 xxxx nnnn mmmm xxxx 15 0 xxxx dddd dddd dddd d format 15 0 xxxx xxxx dddd dddd ...

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Section 2 CPU Instruction Formats i format 15 0 xxxx xxxx iiii iiii ni format 15 0 xxxx nnnn iiii iiii ni3 format 15 0 xxxx xxxx nnnn x iii ni20 format 32 16 xxxx nnnn iiii xxxx 15 0 ...

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Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 13 MOV MOVA MOVI20 MOVI20S MOVML MOVMU MOVRT MOVT MOVU NOTT PREF ...

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Section 2 CPU Operation Classification Types Code Arithmetic 26 ADD operations ADDC ADDV CMP/cond Comparison CLIPS CLIPU DIVS DIVU DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULR MULS MULU NEG NEGC SUB SUBC SUBV Rev. 3.00 Sep. ...

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Operation Classification Types Code Logic 6 AND operations NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR RTS RTV/N Function ...

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Section 2 CPU Operation Classification Types Code System 14 CLRT control CLRMAC LDBANK LDC LDS NOP RESBANK Register restoration from register bank RTE SETT SLEEP STBANK STC STS TRAPA Floating-point 19 FABS instructions FADD FCMP FCNVDS FCNVSD FDIV FLDI0 FLDI1 ...

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Operation Classification Types Code Floating-point 19 FSCHG instructions FSQRT FSTS FSUB FTRC FPU-related 2 LDS CPU STS instructions Bit 10 BAND manipulation BCLR BLD BOR BSET BST BXOR BANDNOT Bit NOT AND BORNOT BLDNOT Total: 112 Function SZ bit inversion ...

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Section 2 CPU The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order. [Legend] ...

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Data Transfer Instructions Table 2.11 Data Transfer Instructions Instruction Instruction Code 1110nnnniiiiiiii imm → sign extension → Rn MOV #imm,Rn 1001nnnndddddddd (disp × PC) → sign MOV.W @(disp,PC),Rn 1101nnnndddddddd (disp × PC) → Rn MOV.L ...

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Section 2 CPU Instruction Instruction Code 0000nnnnmmmm0110 Rm → (R0 + Rn) MOV.L Rm,@(R0,Rn) 0000nnnnmmmm1100 (R0 + Rm) → MOV.B @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → MOV.W @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn MOV.L @(R0,Rm),Rn 11000000dddddddd R0 → (disp ...

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Instruction Instruction Code MOV.L @(disp12,Rm),Rn 0011nnnnmmmm0001 0110dddddddddddd 11000111dddddddd disp × → R0 MOVA @(disp,PC),R0 MOVI20 #imm20,Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii MOVI20S #imm20,Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii 0100mmmm11110001 R15-4 → R15, Rm → (R15) MOVML.L Rm,@-R15 0100nnnn11110101 (R15) → R0, R15 + ...

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Section 2 CPU Instruction Instruction Code MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 1000dddddddddddd MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 1001dddddddddddd 0000000001101000 ~T → T NOTT 0000nnnn10000011 (Rn) → operand cache PREF @Rn 0110nnnnmmmm1000 Rm → swap lower 2 bytes → SWAP.B Rm,Rn 0110nnnnmmmm1001 Rm → swap ...

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Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT ...

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Section 2 CPU Instruction Instruction Code CLIPS.B Rn 0100nnnn10010001 CLIPS.W Rn 0100nnnn10010101 CLIPU.B Rn 0100nnnn10000001 CLIPU.W Rn 0100nnnn10000101 DIV1 Rm,Rn 0011nnnnmmmm0100 DIV0S Rm,Rn 0010nnnnmmmm0111 DIV0U 0000000000011001 DIVS R0,Rn 0100nnnn10010100 DIVU R0,Rn 0100nnnn10000100 DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn ...

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Instruction Instruction Code EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULR R0,Rn 0100nnnn10000000 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV ...

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Section 2 CPU 2.4.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Instruction Instruction Code AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0,GBR) 11001101iiiiiiii NOT Rm,Rn 0110nnnnmmmm0111 OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0,GBR) 11001111iiiiiiii TAS.B @Rn 0100nnnn00011011 TST ...

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Shift Instructions Table 2.14 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAD Rm,Rn 0100nnnnmmmm1100 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLD Rm,Rn 0100nnnnmmmm1101 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 ...

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Section 2 CPU 2.4.6 Branch Instructions Table 2.15 Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 ...

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System Control Instructions Table 2.16 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDBANK @Rm,R0 0100mmmm11100101 LDC Rm,SR 0100mmmm00001110 LDC Rm,TBR 0100mmmm01001010 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 ...

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Section 2 CPU Instruction Instruction Code STC GBR,Rn 0000nnnn00010010 STC VBR,Rn 0000nnnn00100010 STC.L SR,@-Rn 0100nnnn00000011 STC.L GBR,@-Rn 0100nnnn00010011 STC.L VBR,@-Rn 0100nnnn00100011 STS MACH,Rn 0000nnnn00001010 STS MACL,Rn 0000nnnn00011010 STS PR,Rn 0000nnnn00101010 STS.L MACH,@-Rn 0100nnnn00000010 STS.L MACL,@-Rn 0100nnnn00010010 STS.L PR,@-Rn 0100nnnn00100010 TRAPA ...

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Floating-Point Operation Instructions Table 2.17 Floating-Point Operation Instructions Instruction Instruction Code FABS FRn 1111nnnn01011101 FABS DRn 1111nnn001011101 FADD FRm, FRn 1111nnnnmmmm0000 FADD DRm, DRn 1111nnn0mmm00000 FCMP/EQ FRm, FRn 1111nnnnmmmm0100 FCMP/EQ DRm, DRn 1111nnn0mmm00100 FCMP/GT FRm, FRn 1111nnnnmmmm0101 FCMP/GT DRm, ...

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Section 2 CPU Instruction Instruction Code FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 FMOV.S @Rm+, FRn 1111nnnnmmmm1001 FMOV.D @Rm+, DRn 1111nnn0mmmm1001 FMOV.S @Rm, FRn 1111nnnnmmmm1000 FMOV.D @Rm, DRn 1111nnn0mmmm1000 FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd ...

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Instruction Instruction Code FSUB DRm, DRn 1111nnn0mmm00001 FTRC FRm, FPUL 1111mmmm00111101 FTRC DRm, FPUL 1111mmm000111101 2.4.9 FPU-Related CPU Instructions Table 2.18 FPU-Related CPU Instructions Instruction Instruction Code LDS Rm,FPSCR 0100mmmm01101010 LDS Rm,FPUL 0100mmmm01011010 LDS.L @Rm+, FPSCR 0100mmmm01100110 LDS.L @Rm+, FPUL ...

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Section 2 CPU 2.4.10 Bit Manipulation Instructions Table 2.19 Bit Manipulation Instructions Instruction BAND.B #imm3,@(disp12,Rn) BANDNOT.B #imm3,@(disp12,Rn) BCLR.B #imm3,@(disp12,Rn) BCLR #imm3,Rn BLD.B #imm3,@(disp12,Rn) BLD #imm3,Rn BLDNOT.B #imm3,@(disp12,Rn) BOR.B #imm3,@(disp12,Rn) BORNOT.B #imm3,@(disp12,Rn) BSET.B #imm3,@(disp12,Rn) BSET #imm3,Rn BST.B #imm3,@(disp12,Rn) BST #imm3,Rn Rev. ...

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Instruction Instruction Code BXOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0110dddddddddddd Execu- tion Operation Cycles T Bit (imm of (disp + Rn → Rev. 3.00 Sep. 28, 2009 Page 89 of 1650 Section 2 CPU Compatibility SH2, SH2E SH4 SH-2A ...

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Section 2 CPU 2.5 Processing States The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Manual reset from any state Manual reset state Interrupt source or DMA ...

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Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources ...

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Section 2 CPU Rev. 3.00 Sep. 28, 2009 Page 92 of 1650 REJ09B0313-0300 ...

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Section 3 Floating-Point Unit (FPU) 3.1 Features The FPU has the following features. • Conforms to IEEE754 standard • 16 single-precision floating-point registers (can also be referenced as eight double-precision registers) • Two rounding modes: Round to nearest and round ...

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Section 3 Floating-Point Unit (FPU) 3.2 Data Formats 3.2.1 Floating-Point Format A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) This LSI can handle single-precision and double-precision floating-point numbers, using the ...

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Table 3.1 Floating-Point Number Formats and Parameters Parameter Single-Precision Total bit width 32 bits Sign bit 1 bit Exponent field 8 bits Fraction field 23 bits Precision 24 bits Bias +127 E +127 max E –126 min Floating-point number value ...

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Section 3 Floating-Point Unit (FPU) Table 3.2 shows the ranges of the various numbers in hexadecimal notation. Table 3.2 Floating-Point Ranges Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized ...

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Non-Numbers (NaN) Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit ...

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Section 3 Floating-Point Unit (FPU) 3.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. In the SH2A-FPU, the DN bit in the status register FPSCR ...

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Register Descriptions 3.3.1 Floating-Point Registers Figure 3.4 shows the floating-point register configuration. There are sixteen 32-bit floating-point registers FPR0 to FPR15, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14. The correspondence between FRPn and the reference name is determined by ...

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Section 3 Floating-Point Unit (FPU) 3.3.2 Floating-Point Status/Control Register (FPSCR) FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Bit Initial value ...

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Initial Bit Bit Name Value Cause All Enable All Flag All 0 1 RM1 0 0 RM0 1 Table 3.3 Bit Allocation for FPU Exception Handling Field Name Cause ...

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Section 3 Floating-Point Unit (FPU) 3.4 Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC will differ from the result when using ...

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FPU Exceptions 3.5.1 FPU Exception Sources FPU exceptions may be triggered by floating point operation instructions. The exception sources are as follows: • FPU error (E): When FPSCR. and a denormalized number is input (No error occurs ...

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Section 3 Floating-Point Unit (FPU) The possibilities for exception handling caused by floating point operations are described in the individual instruction descriptions. All exception events that originate in floating point operations are assigned as the same FPU exception handling event. ...

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Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, and divider ...

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Section 4 Clock Pulse Generator (CPG) Figure 4.1 shows a block diagram of the clock pulse generator. Divider 1 × 1 × 1/2 × 1/4 Crystal XTAL oscillator EXTAL Crystal USB_X2 oscillator USB_X1 CKIO MD_CLK1 Clock frequency control circuit MD_CLK0 ...

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The clock pulse generator blocks function as follows: (1) Crystal Oscillator The crystal oscillator is used in which the crystal resonator is connected to the XTAL/EXTAL pin or USB_X1/USB_X2 pin. One of them is selected according to the clock operating ...

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Section 4 Clock Pulse Generator (CPG) 4.2 Input/Output Pins Table 4.1 lists the clock pulse generator pins and their functions. Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol I/O Mode MD_ Input control pins ...

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Clock Operating Modes Table 4.2 shows the relationship between the combinations of the mode control pins (MD_CLK1 and MD_CLK0) and the clock operating modes. Table 4.3 shows the usable frequency ranges in the clock operating modes. Table 4.2 Clock ...

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Section 4 Clock Pulse Generator (CPG) • Mode 2 In mode 2, the CKIO pin functions as an input pin and draws an external clock signal. The PLL circuit shapes waveform and the frequency is multiplied according to the frequency ...

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Table 4.3 Relationship between Clock Operating Mode and Frequency Range PLL Frequency Multiplier Clock Operating FRQCR PLL 1 Mode Setting* Circuit 0 H'x003 ON (× 8) H'x004 ON (× 8) H'x005 ON (× 8) H'x006 ON (× 8) H'x104 ON ...

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Section 4 Clock Pulse Generator (CPG) PLL Frequency Ratio of Multiplier Clock Internal Clock Operating FRQCR Frequencies PLL 1 (I:B:P)* Mode Setting* Circuit 2 H'x206 ON (× 16) 4:1:1/3 H'x215 ON (× 16) 2:1:1/2 H'x216 ON (× 16) 2:1:1/3 3 ...

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Register Descriptions The clock pulse generator has the following registers. Table 4.4 Register Configuration Register Name Frequency control register 4.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from ...

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Section 4 Clock Pulse Generator (CPG) Initial Bit Bit Name Value 14 CKOEN2 0 13, 12 CKOEN[1:0] 00 ⎯ 11, 10 All STC[1:0] 00 Rev. 3.00 Sep. 28, 2009 Page 114 of 1650 REJ09B0313-0300 R/W Description R/W ...

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Initial Value Bit Bit Name ⎯ All 0 4 IFC 0 ⎯ PFC[2:0] 011 Table 4.5 CKOEN[1:0] Settings Normal Operation Setting 00 Output 01 Output 10 Output 11 Output off (Hi-Z) R/W ...

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Section 4 Clock Pulse Generator (CPG) 4.5 Changing the Frequency The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by changing the multiplication rate of PLL circuit or by changing the division rates of ...

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Changing the Division Ratio Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not the initial state, IFC = B'0 and PFC[2:0] = B'011. 2. Set the desired value ...

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Section 4 Clock Pulse Generator (CPG) 4.6 Usage of the Clock Pins For the connection of a crystal resonator or the input of a clock signal, this LSI circuit has the pins listed in table 4.6. With regard to these ...

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In the Case of Using a Crystal Resonator An example of the connection of crystal resonator is shown in figure 4.3. Place the crystal resonator and capacitors (CL1 and CL2) as close to pins Xin and Xout as possible. ...

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Section 4 Clock Pulse Generator (CPG) 4.7 Oscillation Stabilizing Time 4.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator In the case of using a crystal resonator, please wait longer than the oscillation stabilizing time at the following cases, to ...

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Notes on Board Design 4.8.1 Note on Using a PLL Oscillation Circuit In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width ...

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Section 4 Clock Pulse Generator (CPG) 4.9 Usage Note When this LSI is used in clock mode the CKIO output will be unstable for one cycle after negation of the RES signal. Rev. 3.00 Sep. 28, ...

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Section 5 Exception Handling 5.1 Overview 5.1.1 Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling sources ...

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Section 5 Exception Handling Type Exception Handling Interrupt On-chip peripheral modules I Instruction Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed branch instruction* instructions in FPU module standby state), ...

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Exception Handling Operations The exception handling sources are detected and start processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Reset Power-on reset Manual reset ...

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Section 5 Exception Handling Exception Source Instructions FPU exception When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the ...

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Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the ...

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Section 5 Exception Handling Exception Sources Integer division exception (division by zero) Integer division exception (overflow) (Reserved by system) Trap instruction (user vector) External interrupts (IRQ, PINT), on-chip peripheral module interrupts* Note: * The vector numbers and vector table address ...

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Resets 5.2.1 Input/Output Pins Table 5.5 shows the reset-related pin configuration. Table 5.5 Pin Configuration Pin Name Symbol RES Power-on reset MRES Manual reset 5.2.2 Types of Reset A reset is the highest-priority exception handling source. There are two ...

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Section 5 Exception Handling 5.2.3 Power-On Reset Power-On Reset by Means of RES Pin (1) When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept ...

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Power-On Reset Initiated by WDT When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, ...

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Section 5 Exception Handling 5.2.4 Manual Reset Manual Reset by Means of MRES Pin (1) When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without fail, the MRES pin should be ...

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Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.7. Table 5.7 Bus Cycles and Address Errors Bus Cycle Bus Type Master Bus Cycle Description Instruction ...

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Section 5 Exception Handling 5.3.2 Address Error Exception Handling When an address error occurs, the bus cycle in which the address error occurred ends.* When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: ...

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Register Bank Errors 5.4.1 Register Bank Error Sources (1) Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by ...

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Section 5 Exception Handling 5.5 Interrupts 5.5.1 Interrupt Sources Table 5.8 shows the sources that start interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules. Table 5.8 Interrupt Sources Type NMI User ...

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Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts is expressed as priority ...

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Section 5 Exception Handling 5.5.3 Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than ...

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Exceptions Triggered by Instructions 5.6.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, slot illegal instructions, general illegal instructions, integer division exceptions, and FPU exceptions, as shown in table 5.10. Table 5.10 Types ...

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Section 5 Exception Handling 5.6.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA ...

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General Illegal Instructions When an undefined code, including FPU instructions and FPU-related CPU instructions in FPU module standby state, placed anywhere other than immediately after a delayed branch instruction, i.e delay slot, is decoded, general illegal instruction ...

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Section 5 Exception Handling 5.6.6 FPU Exceptions FPU exception handling takes place when the bit in the FPU enable field (Enable) of the floating point status/control register (FPSCR) is set to 1. This indicates ...

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When Exception Sources Are Not Accepted When an address error, FPU exception, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction sometimes not accepted immediately but stored instead, as shown in table ...

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Section 5 Exception Handling 5.8 Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 5.12. Table 5.12 Stack Status After Exception Handling Ends Exception Type Address error Interrupt Register ...

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Exception Type General illegal instruction Integer division exception FPU exception Section 5 Exception Handling Stack Status Start address of general SP illegal instruction SR Start address of relevant SP integer division instruction SR Address of instruction SP after executed instruction ...

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Section 5 Exception Handling 5.9 Usage Notes 5.9.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed ...

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Note before Exception Handling Begins Running Before exception handling begins running, the exception handling vector table must be stored in a memory, and the CPU must be able to access the memory. So, if the exception handling is generated ...

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Section 5 Exception Handling Rev. 3.00 Sep. 28, 2009 Page 148 of 1650 REJ09B0313-0300 ...

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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests ...

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Section 6 Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ7 to IRQ0 Input control PINT7 to PINT0 (Interrupt request) UBC (Interrupt request) H-UDI (Interrupt request) DMAC (Interrupt request) USB (Interrupt request) LCDC (Interrupt ...

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Input/Output Pins Table 6.1 shows the pin configuration of the INTC. Table 6.1 Pin Configuration Pin Name Nonmaskable interrupt input pin Interrupt request input pins Interrupt request output pin Symbol I/O Function NMI Input Input of nonmaskable interrupt request ...

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Section 6 Interrupt Controller (INTC) 6.3 Register Descriptions The INTC has the following registers. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 6.2 Register Configuration Register Name Interrupt control ...

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Interrupt Priority Registers 01, 02 (IPR01, IPR02, IPR05 to IPR17) IPR01, IPR02, and IPR05 to IPR17 are 16-bit readable/writable registers in which priority levels from are set for IRQ interrupts, PINT interrupts, and ...

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Section 6 Interrupt Controller (INTC) Register Name Bits Interrupt priority IIC3-3 register 13 Interrupt priority SCIF3 register 14 Interrupt priority SSI1 register 15 Interrupt priority FLCTL register 16 Interrupt priority RCAN1 register 17 As shown in table ...

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Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. Bit NMIL ...

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Section 6 Interrupt Controller (INTC) 6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. Bit: ...

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Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7 to PINT0 individually: low level or high level. Bit ...

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Section 6 Interrupt Controller (INTC) 6.3.5 IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 ...

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Initial Bit Bit Name Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 [Legend R/W Description IRQ Interrupt Request ...

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Section 6 Interrupt Controller (INTC) 6.3.6 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit register that enables interrupt request inputs to external interrupt input pins PINT7 to PINT0. Bit ...

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PINT Interrupt Request Register (PIRR) PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. Bit Initial value: R/ ...

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Section 6 Interrupt Controller (INTC) 6.3.8 Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. Bit E15 E14 E13 E12 ...

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Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to ...

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Section 6 Interrupt Controller (INTC) Initial Bit Bit Name Value BN[3:0] 0000 Rev. 3.00 Sep. 28, 2009 Page 164 of 1650 REJ09B0313-0300 R/W Description R Bank Number These bits indicate the bank number to which saving is ...

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Interrupt Sources There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to ...

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Section 6 Interrupt Controller (INTC) checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 ...

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On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following on-chip peripheral modules: • Direct memory access controller (DMAC) • USB2.0 host/function module (USB) • LCD controller (LCDC) • Compare match timer (CMT) • Bus state ...

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Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Handling Vector Table and Priority Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector ...

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