R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 838

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 16 Synchronous Serial Communication Unit (SSU)
16.3.8
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. The
SSRDR that has not been enabled must not be accessed.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR
function as a double buffer in this way, consecutive receive operations can be performed.
Read SSRDR after confirming that the RDRF bit in SSSR is set to 1.
SSRDR is a read-only register, therefore, cannot be written to by the CPU.
Table 16.4 Correspondence between DATS Bit Setting and SSRDR
Rev. 3.00 Sep. 28, 2009 Page 806 of 1650
REJ09B0313-0300
Bit
7 to 0
SSRDR
0
1
2
3
Bit Name
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
00
Valid
Invalid
Invalid
Invalid
Initial value:
Initial
Value
All 0
R/W:
Bit:
R/W
R
R
7
0
01
Valid
Valid
Invalid
Invalid
R
6
0
Description
Serial receive data
R
5
0
DATS[1:0] (SSCRL[1:0])
R
4
0
R
3
0
10
Valid
Valid
Valid
Valid
R
2
0
R
1
0
11 (Setting Disabled)
Invalid
Invalid
Invalid
Invalid
R
0
0