R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 221

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

The contents of the general registers (R0 to R14), global base register (GBR), multiply and

accumulate registers (MACH and MACL), and procedure register (PR), and the vector table

address offset are banked.

This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in last-

out (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes

place in the reverse order, beginning from the last bank saved to.

Figure 6.11 shows register bank save operations. The following operations are performed when an

interrupt for which usage of register banks is allowed is accepted by the CPU:

a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the

b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector

c. The BN value is incremented by 1.

interrupt is generated.

table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN,

Banked Register

Input/Output of Banks

Saving to Bank

Banked Register and Input/Output of Banks

Bank Save and Restore Operations

Figure 6.11 Bank Save Operations

Rev. 3.00 Sep. 28, 2009 Page 189 of 1650

Section 6 Interrupt Controller (INTC)

REJ09B0313-0300