R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 373

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of

latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.

When bank active mode is set, if only access cycles to the respective banks in the area 3 space are

considered, as long as access cycles to the same row address continue, the operation starts with the

cycle in figure 9.22 or 9.25, followed by repetition of the cycle in figure 9.23 or 9.26. An access to

a different area during this time has no effect. If there is an access to a different row address in the

bank active state, the bus cycle in figure 9.24 or 9.27 is executed instead of that in figure 9.23 or

9.26. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is

released as the result of bus arbitration.

Figure 9.22 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)

Notes: 1. Address pin to be connected to pin A10 of SDRAM.

2. The waveform for DACKn is when active low is specified.

Rev. 3.00 Sep. 28, 2009 Page 341 of 1650

Section 9 Bus State Controller (BSC)

REJ09B0313-0300