R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 657

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4

to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is

In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA

and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3

functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer

The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are

operating as buffer registers.

Figure 11.109 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with

TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.

TGRB_3, TGRA_4,

TGRD_3, TGRC_4,

Figure 11.109 Buffer Operation and Compare-Match Flags

in Reset Synchronous PWM Mode

Buffer transfer with

compare match A3

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 3.00 Sep. 28, 2009 Page 625 of 1650

TGRB_3, TGRD_3,

TGRA_4, TGRC_4,

TGRB_4, TGRD_4

REJ09B0313-0300