R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 297

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bit
31 to 22
21
20
19
Bit Name
⎯
SZSEL
MPXW
BAS
⎯
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MPX-I/O Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BCR are specified as 11. This bit is
valid only when area 5 is specified as MPX-I/O.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus width
selected by A14 or A21 are summarized below.
SZSEL
0
0
1
1
MPX-I/O Interface Address Wait
This bit setting is valid only when area 5 is specified as
MPX-I/O. Specifies the address cycle insertion wait for
MPX-I/O interface.
0: Inserts no wait cycle
1: Inserts 1 wait cycle
SRAM with Byte Selection Byte Access Select
This bit setting is valid only when area 5 is specified as
SRAM with byte selection.
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read access cycle
Reserved
This bit is always read as 0. The write value should
always be 0.
asserts the RD/WR signal during the write access
cycle.
and asserts the RD/WR signal at the write timing.
A14
0
1
Not affected
Not affected
Rev. 3.00 Sep. 28, 2009 Page 265 of 1650
Section 9 Bus State Controller (BSC)
A21
Not affected
Not affected
0
1
REJ09B0313-0300
Bus Width
8 bits
16 bits
8 bits
16 bits