R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 386
![KIT DEV FOR SH7203](/photos/9/24/92406/r0k572030s000be_sml.jpg)
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
- Current page: 386 of 1686
- Download datasheet (10Mb)
Section 9 Bus State Controller (BSC)
(12) Power-On Sequence
In order to use SDRAM, mode setting must first be made for SDRAM after waiting for the
designated pause interval after powering on. This pause interval should be provided by a power-on
reset generating circuit or software.
To perform SDRAM initialization correctly, the bus state controller registers must first be set,
followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address
signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL,
and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be
written to the SDRAM mode register by performing a write to address H'FFFC4000 + X for area 2
SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is
ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS
latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is
written in a byte-size access to the addresses shown in table 9.18. In this time 0 is output at the
external address pins of A12 or later.
Table 9.18 Access Address in SDRAM Mode Register Write
• Setting for Area 2
Rev. 3.00 Sep. 28, 2009 Page 354 of 1650
REJ09B0313-0300
Data Bus Width
16 bits
32 bits
Data Bus Width
16 bits
32 bits
Burst read/single write (burst length 1):
Burst read/burst write (burst length 1):
CAS Latency
2
3
2
3
CAS Latency
2
3
2
3
Access Address
H'FFFC4440
H'FFFC4460
H'FFFC4880
H'FFFC48C0
Access Address
H'FFFC4040
H'FFFC4060
H'FFFC4080
H'FFFC40C0
External Address Pin
H'0000440
H'0000460
H'0000880
H'00008C0
External Address Pin
H'0000040
H'0000060
H'0000080
H'00000C0
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