R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 889

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs

the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,

refer to figures 17.9 and 17.10.

The transmission procedure and operations in slave transmit mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and

2. When the slave address matches in the first frame following detection of the start condition,

3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,

4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened.

5. Clear TDRE.

TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit

in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The

continuous transmission is performed by writing transmit data to ICDRT every time TDRE is

with TDRE = 1. When TEND is set, clear TEND.

Slave Transmit Operation

Rev. 3.00 Sep. 28, 2009 Page 857 of 1650

Section 17 I

C Bus Interface 3 (IIC3)

REJ09B0313-0300