R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 448

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 10 Direct Memory Access Controller (DMAC)
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If
fixed mode 2 is specified, the channel priority is specified as CH0 > CH4 > CH1 > CH5 > CH2 >
CH6 > CH3 > CH7. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 >
CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If the round-robin mode is specified, the transfer end
channel is reset.
Table 10.3 show the priority change in each mode (modes 0 to 2) specified by the priority mode
bits. In each priority mode, the channel priority to accept the next transfer request may change in
up to three ways according to the transfer end channel.
For example, when the transfer end channel is channel 1, the priority of the channel to accept the
next transfer request is specified as CH2 > CH3 > CH0 >CH1 > CH4 > CH5 > CH6 > CH7. When
the transfer end channel is any one of the channels 4 to 7, round-robin will not be applied and the
priority level is not changed at the end of transfer in the channels 4 to 7.
The DMAC internal operation for an address error is as follows:
• No address error: Read (source to DMAC) → Write (DMAC to destination)
• Address error in source address: Nop → Nop
• Address error in destination address: Read → Nop
Rev. 3.00 Sep. 28, 2009 Page 416 of 1650
REJ09B0313-0300
Bit
0
2. If the flag is read at the same timing it is set to 1, the read data will be 0, but the internal
Bit Name
DME
state may be the same as reading 1. Therefore, if 0 is written to the flag, the flag will be
cleared to 0 because the internal state is the same as when writing 0 after reading 1.
For details, refer to section 10.5.5, Notes on Using Flag Bits.
Initial
Value
0
R/W
R/W
Description
DMA Master Enable
Enables or disables DMA transfer on all channels. If
the DME bit and DE bit in CHCR are set to 1, DMA
transfer is enabled.
However, transfer is enabled only when the TE bit in
CHCR of the transfer corresponding channel, the NMIF
bit in DMAOR, and the AE bit are all cleared to 0.
Clearing the DME bit to 0 can terminate the DMA
transfer on all channels.
0: DMA transfer is disabled on all channels
1: DMA transfer is enabled on all channels