R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1038

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Section 19 Controller Area Network (RCAN-TL1)
The following settings were used in the above example:
CMAX = 3'b011, TXPR[30] = 0
During merged arbitrating window, request by time-triggered transmission is served in the way of
FCFS (First Come First Served). For example, if Mailbox-25 cannot be transmitted between Tx-
Trigger Time 25 (TTT25) and TTT26, Mailbox-25 has higher priority than Mailbox-26 between
TTT26 and 28.
MBC needs to be set into 3'b111, in order to disable time-triggered transmission. If RCAN-TL1 is
Time Master, MBC[30] has to be 3'b000 and time reference window is automatically recognized
as arbitrating window.
• Timer Operation
Figure 19.23 shows the timing diagram of the timer. By setting Tx-Trigger Time = n, time trigger
transmission starts between CYCTR = n + 2 and
CYCTR = n + 3.
Rev. 3.00 Sep. 28, 2009 Page 1006 of 1650
REJ09B0313-0300
Mailbox-24
Mailbox-25
Mailbox-26
Mailbox-27
Mailbox-28
Mailbox-29
Mailbox-30
Mailbox-31
rep_factor
(register)
3'b001
3'b000
3'b000
3'b000
3'b010
3'b011
Offset
6'b000000
6'b000000
6'b000000
6'b000000
6'b000001
6'b000110
TTW[1:0]
2'b00
2'b10
2'b10
2'b11
2'b00
2'b01
MBC[2:0]
3'b000
3'b000
3'b000
3'b000
3'b000
3'b000
3'b111
3'b011

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