R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1297

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Notes: 1. Write H'0011 to LDCNTR to start display output and H'0000 to end display output. Data
24.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)
LDUINTR sets whether the user specified interrupt is generated, and indicates its processing state.
This interrupt is generated at the time when image data which is set by the line number register
(LDUINTLNR) in LCDC is read from VRAM.
This LCDC issues the interrupts (LCDCI): user specified interrupt by this register, memory access
interrupt by the LCDC interrupt control register (LDINTR), and OR of Vsync interrupt output.
This register and LCDC interrupt control register (LDINTR) settings affect the interrupt operation
independently.
Initial value:
Bit
0
Bit
15 to 9
R/W:
Bit:
2. Setting bit DON2 to 1 makes the contents of the palette RAM undefined. Before writing
3. After writing to LDCNTR, it takes some time for the display to actually start or stop.
15
R
0
Bit Name
DON
-
Bit Name
⎯
other than H'0011 and H'0000 must not be written here.
to the palette RAM, set bit DON2 to 1.
Thus, to access another register of the LCDC after writing to LDCNTR, dummy-read
LDCNTR once beforehand.
14
R
0
-
13
R
0
-
Initial
Value
0
Initial
Value
All 0
12
R
0
-
11
R
0
-
R/W
R/W
R/W
R
10
R
0
-
Display On
Description
Specifies the start and stop of the LCDC display
operation.
The control sequence state can be checked by
referencing the LPS[1:0] of LDPMMR.
0: Display-off mode: LCDC is stopped
1: Display-on mode: LCDC operates
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
R
9
0
-
UINTEN
R/W
8
0
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1265 of 1650
R
6
0
-
R
Section 24 LCD Controller (LCDC)
5
0
-
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
R
1
0
-
UNITS
R/W
0
0