R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 425

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1
• Number of channels: Eight channels (channels 0 to 7) selectable
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests
• Selectable bus modes
• Selectable channel priority levels: The channel priority levels are selectable between fixed
• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-
Four channels (channels 0 to 3) can receive external requests.
(longword × 4)
⎯ External request
⎯ On-chip peripheral module request
⎯ Auto request
The following modules can issue on-chip peripheral module requests.
⎯ Eight SCIF sources, eight IIC3 sources, one A/D converter source, five MTU2 sources, two
⎯ Cycle steal mode (normal mode and intermittent mode)
⎯ Burst mode
mode and round-robin mode.
data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to
the CPU when half of the initially specified DMA transfer is completed.
Section 10 Direct Memory Access Controller (DMAC)
CMT sources, two USB sources, two FLCTL sources, two RCAN-TL1 sources, four SSI
sources, four SSU sources
Features
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 393 of 1650
REJ09B0313-0300