R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1160

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
23.3.12 Interrupt Enabled Register 1 (INTENB1)
INTENB1 is a register that specifies the masking of various interrupts and controls the BRDY
interrupt status clear timing.
This register is initialized by a power-on reset. By a software reset, bits other than BRDYM are
initialized.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1128 of 1650
REJ09B0313-0300
Bit
15
14
13
12
R/W:
Bit:
Bit Name
⎯
BCHGE
⎯
DTCHE
15
R
0
-
BCHGE
R/W
14
0
13
R
0
-
DTCHE
Initial
Value
0
0
0
0
R/W
12
0
11
R
0
-
R/W
R
R/W
R
R/W
10
R
0
-
R
9
0
-
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
USB Bus Change Interrupt Enable
0: Interrupt output disabled
1: Interrupt output enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
Disconnection Detection Interrupt Enable during Full-
Speed Operation
The disconnection detection using this bit is valid
only when the host controller function is selected and
full-speed operation is performed. During high-speed
operation, software should be used to detect
disconnection by detecting no response from a
function or by another appropriate method.
0: Interrupt output disabled
1: Interrupt output enabled
Note: When high-speed operation established
R
8
0
-
(RHST = 11) is determined after a reset
handshake, keep DTCHE cleared to 0 during
high-speed communication.
R
7
0
-
R
6
0
-
SIGNE SACKE
R/W
5
0
R/W
4
0
R
3
0
-
BRDYM
R/W
2
0
R
1
0
-
R
0
0
-