R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1301

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per

pixel). The image data for display is stored in VRAM, which is shared with the CPU. This LCDC

should read the data from VRAM before display.

This LSI has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although

a complete breakdown of the display is unlikely, there may be some problems with the display

depending on the combination.

As a rough standard, the bus occupation ratio shown below should not exceed 40%.

The overhead coefficient becomes 1.375 when the CL2 SDRAM is connected to a 32-bit data bus

and 1.188 when connected to a 16-bit data bus.

Bus occupation ratio (%) =

LCD Module Sizes which Can Be Displayed in this LCDC

Overhead coefficient x Total number of display pixels ((HDCN + 1) x 8 x (VDLN + 1))

x Frame rate (Hz) x Number of colors (bpp)

CKIO (Hz) x Bus width (bit)

Rev. 3.00 Sep. 28, 2009 Page 1269 of 1650

Section 24 LCD Controller (LCDC)

REJ09B0313-0300