R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1017

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Timer Clear-Set:
The Timer value can only be cleared when a Compare Match occurs if it is enabled by the Bit6 in
the TTCR0. TCMR1 and TCMR2 do not have this function.
Cancellation of the messages in the transmission queue:
The messages in the transmission queue can only be cleared by the TCMR2 through setting TXCR
when a Compare Match occurs while RCAN-TL1 is not in the halt status. TCMR1 and TCMR0 do
not have this function.
• TCMR0 (Address = H'098)
Bits 15 to 0 — Timer Compare Match Register (TCMR0): Indicates the value of TCNTR when
compare match occurs.
• TCMR1 (Address = H'09C)
Bits 15 to 0 — Timer Compare Match Register (TCMR1): Indicates the value of CYCTR
when compare match occurs.
• TCMR2 (Address = H'0A0)
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
R/W
R/W
R/W
15
15
15
1
1
1
R/W
R/W
R/W
14
14
14
1
1
1
R/W
R/W
R/W
13
13
13
1
1
1
R/W
R/W
R/W
12
12
12
1
1
1
R/W
R/W
R/W
11
11
11
1
1
1
R/W
R/W
R/W
10
10
10
1
1
1
R/W
R/W
R/W
9
1
9
1
9
1
R/W
R/W
TCMR1[15:0]
R/W
TCMR0[15:0]
TCMR2[15:0]
8
1
8
1
8
1
Section 19 Controller Area Network (RCAN-TL1)
R/W
R/W
R/W
7
1
7
1
7
1
Rev. 3.00 Sep. 28, 2009 Page 985 of 1650
R/W
R/W
R/W
6
1
6
1
6
1
R/W
R/W
R/W
5
1
5
1
5
1
R/W
R/W
R/W
4
1
4
1
4
1
R/W
R/W
R/W
3
1
3
1
3
1
R/W
R/W
REJ09B0313-0300
R/W
2
1
2
1
2
1
R/W
R/W
R/W
1
1
1
1
1
1
R/W
R/W
R/W
0
1
0
1
0
1