R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1218

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
(5)
Figure 23.7 shows a diagram of how this module handles the control transfer stage transition. This
module controls the control transfer sequence and generates control transfer stage transition
interrupts. Control transfer stage transition interrupts can be enabled or disabled individually using
INTENB0. The transfer stage that made a transition can be confirmed using the CTSQ bit in
INTSTS0.
The control transfer sequence errors are described below. If an error occurs, the PID bit in
DCPCTR is set to B'1x (STALL).
1. During control read transfers
2. During control write transfers
3. During no-data control transfers
At the control write transfer stage, if the number of receive data exceeds the wLength value of the
USB request, it cannot be recognized as a control transfer sequence error. At the control read
transfer status stage, packets other than zero-length packets are received by an ACK response and
the transfer ends normally.
When a CTRT interrupt occurs in response to a sequence error (SERR = 1), the CTSQ = 110 value
is retained until CTRT = 0 is written from the system (the interrupt status is cleared). Therefore,
while CTSQ = 110 is being held, the CTRT interrupt that ends the setup stage will not be
generated even if a new USB request is received. (This module retains the setup stage end, and
after the interrupt status has been cleared by software, a setup stage end interrupt is generated.)
Rev. 3.00 Sep. 28, 2009 Page 1186 of 1650
REJ09B0313-0300
⎯ At the IN token of the data stage, an OUT or PING token is received when there have been
⎯ An IN token is received at the status stage
⎯ A packet is received at the status stage for which the data packet is DATAPID = DATA0
⎯ At the OUT token of the data stage, an IN token is received when there have been no ACK
⎯ A packet is received at the data stage for which the first data packet is DATAPID =
⎯ At the status stage, an OUT or PING token is received
⎯ At the status stage, an OUT or PING token is received
Control Transfer Stage Transition Interrupt
no data transfers at all.
response at all
DATA0