R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1148

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
23.3.6
CFIFO, D0FIFO and D1FIFO are port registers that are used to read data from the FIFO buffer
memory and writing data to the FIFO buffer memory.
There are three FIFO ports: the CFIFO, D0FIFO and D1FIFO ports. Each FIFO port is configured
of a port register that handles reading of data from the buffer memory and writing of data to the
buffer memory, a select register that is used to select the pipe assigned to the FIFO port, a control
register, and registers used specially for port functions (an SIE register used exclusively for the
CFIFO port and a transaction counter register used exclusively for the DnFIFO port).
These registers are initialized by a power-on reset or a software reset.
Initial value:
Initial value:
Notes: 1. The DCP can access the buffer memory only through the CFIFO port. Accessing the
Rev. 3.00 Sep. 28, 2009 Page 1116 of 1650
REJ09B0313-0300
Bit
31 to 0
R/W:
R/W:
Bit:
Bit:
2. Accessing the DnFIFO port using the CPU must be performed in conjunction with the
3. When using functions specific to the FIFO port, the selected pipe cannot be changed
4. Registers configuring a FIFO port do not affect other FIFO ports.
5. The same pipe should not be assigned to two or more FIFO ports.
6. There are two sorts of buffer memory states: the access right is on the CPU side and it
7. The pipe configuration of the pipe selected for the FIFO port should not be changed.
R/W
R/W
FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)
Bit Name
FIFOPORT
[31:0]
31
15
0
0
buffer memory using DMA transfer can be performed only through the D0FIFO and
D1FIFO ports.
functions and restrictions of the DnFIFO port (using the transaction counter, etc.).
(using the transaction counter, etc.).
is on the SIE side. When the buffer memory access right is on the SIE side, the memory
cannot be properly accessed from the CPU.
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
R/W
R/W
25
0
9
0
Description
FIFO Port
These bits are used to read receive data from the
buffer memory and write transmit data to the buffer
memory.
FIFOPORT[31:16]
FIFOPORT[15:0]
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0