R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1235

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(2)
Table 23.19 shows the settings for the FIFO port functions of this module. In write access, writing
data until the buffer is full (or the maximum packet size for non-continuous transfers)
automatically enables sending of the data. To enable sending of data before the buffer is full (or
before the maximum packet size for non-continuous transfers), the BVAL bit in C/DnFIFOCTR
must be set to end the writing. Also, to send a zero-length packet, the BCLR bit in the same
register must be used to clear the buffer and then the BVAL bit set in order to end the writing.
In read access, reception of new packets is automatically enabled if all of the data has been read.
Data cannot be read when a zero-length packet is being received (DTLN = 0), so the BCLR bit in
the register must be used to release the buffer. The length of the data being received can be
confirmed using the DTLN bit in C/DnFIFOCTR.
Table 23.19 FIFO Port Function Settings
Note:
Register Name
C/DnFIFOSEL
C/DnFIFOCTR
DnFIFOTRN
CFIFOSIE (except
DCP)
FIFO Port Functions
* When CFIFOSEL.CURPIPE = DCP, setting CFIFOCTR.BCLR to 1 also clears the
buffer memory on the SIE side.
Bit Name
REW
DCLRM
DREQE
MBW
TRENB
TRCLR
DEZPM
ISEL
BVAL
BCLR*
DTLN
TRNCNT
TGL
SCLR
Function
Buffer memory rewind (re-read, rewrite
Automatically clears data received for
a specified pipe after the data has
been read
Asserts DREQ signal
FIFO port access bit width
Enables transaction counter operation For DnFIFO only
Clears the current number of
transactions
zero-length packet addition mode
FIFO port access direction
Ends writing to the buffer memory
Clears the buffer memory on the CPU
side
Confirms the length of received data
Sets the received transaction count
CPU/SIE buffer toggle
Clears the buffer memory on the SIE
side
Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1203 of 1650
Note
For DnFIFO only
For DnFIFO only
For DnFIFO only
For DMA only
For DCP only
For DnFIFO only
For CFIFO only
For CFIFO only
REJ09B0313-0300