R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1233

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Table 23.18 Buffer Memory Map
(d)
With this module, all of the received data packets are discarded if the ACLRM bit in PIPEnCTR is
set to 1. If a normal data packet has been received, the ACK response is returned to the host
controller. This function can be set only in the buffer memory reading direction.
Also, if the ACLRM bit is set to 1 and then to 0, the buffer memory of the pipe can be cleared
regardless of the access direction.
An access cycle of at least 100 ns is required between ACLRM = 1 and ACLRM = 0.
(e)
Either a single or double buffer can be selected for PIPE1 to PIPE5, using the DBLB bit in
PIPEnCFG. The double buffer is a function that assigns two memory areas specified with the
BUFSIZE bit in PIPEBUF to the same pipe. Figure 23.10 shows an example of buffer memory
settings for this module.
Buffer Memory
Number
H'0 to H'3
H'4
H'5
H'6 to H'7F
Auto Buffer Clear Mode Function
Buffer Memory Specifications (Single/Double Setting)
Figure 23.10 Example of Buffer Memory Settings
Buffer Size
256 bytes
64 bytes
64 bytes
Up to 7808
bytes
Buffer memory
128 bytes
64 bytes
64 bytes
64 bytes
Pipe Setting
DCP special
fixed area
Fixed area for
PIPE6
Fixed area for
PIPE7
PIPE1 to PIPE5
user area
Section 23 USB 2.0 Host/Function Module (USB)
Note
Single buffer, continuous transfers
enabled
Single buffer
Single buffer
Double buffer can be set, continuous
transfers enabled
PIPEBUF registers
Rev. 3.00 Sep. 28, 2009 Page 1201 of 1650
BUFSIZE = 0,
BUFSIZE = 0,
BUFSIZE = 1,
DBLB = 0
DBLB = 1
DBLB = 0
REJ09B0313-0300