R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 406

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 9 Bus State Controller (BSC)

Figure 9.47 shows an example of a connection between the LSI and the burst MPX device.

Figures 9.48 to 9.51 show the burst MPX space access timings.

Area 6 can be specified as the address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to

TYPE0 bits in CS6BCR. This MPX-I/O interface enables the LSI to be easily connected to an

external memory controller chip that uses an address/data multiplexed 32-bit single bus. In this

case, the address and the access size for the MPX-I/O interface are output to D25 to D0 and D31

to D29, respectively, in address cycles. For the access sizes of D31 to D29, see the description of

CS6WCR for the burst MPX-I/O in section 9.4.3 (5), Burst MPX-I/O.

Address pins A25 to A0 are used to output normal addresses.

In the burst MPX-I/O interface, the bus size is fixed at 32 bits. The BSZ1 and BSZ0 bits in

CS6BCR must be specified as 32 bits. In the burst MPX-I/O interface, a software wait and

hardware wait using the WAIT pin can be inserted.

In read cycles, a wait cycle is inserted automatically following the address output even if the

software wait insertion is specified as 0.

Rev. 3.00 Sep. 28, 2009 Page 374 of 1650

REJ09B0313-0300

Burst MPX-I/O Interface

Figure 9.47 Burst MPX Device Connection Example

64K × 16-bit