R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1012

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 19 Controller Area Network (RCAN-TL1)
(4)
This register is a 16-bit read-only register, and allows the CPU to monitor the Timer Compare
Match status and the Timer Overrun Status.
• TSR (Address = H'088)
Bits 15 to 5: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bits 4 to 0 — RCAN-TL1 Timer Status (TSR[4:0]): This read-only field allows the CPU to
monitor the status of the Cycle Counter, the Timer and the Compare Match registers. Writing to
this field has no effect.
Bit 4 — Start of New System Matrix (TSR4): Indicates that a new system matrix is starting.
When CCR = 0, this bit is set at the successful completion of reception/transmission of time
reference message.
Bit 3 — Timer Compare Match Flag 2 (TSR3): Indicates that a Compare-Match condition
occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the TCMR2
matches to Cycle Time Register (TCMR2 = CYCTR), this bit is set if TTCR0 bit12 = 1. Please
note that this bit is read-only and is cleared when IRR11 (Timer Compare Match Interrupt 2) is
cleared.
Rev. 3.00 Sep. 28, 2009 Page 980 of 1650
REJ09B0313-0300
Bit4: TSR4
0
1
Initial value:
Timer Status Register (TSR)
R/W:
Bit:
15
R
0
-
14
R
0
-
Description
A new system matrix is not starting (initial value)
[Clearing condition] Writing ‘1’ to IRR10 (Cycle Counter Overflow Interrupt)
Cycle counter reached zero
[Setting condition]
When the Cycle Counter value changes from the maximum value (CMAX) to
H'0. Reception/transmission of time reference message is successfully
completed when CMAX!= 3'b111 and CCR = 0
13
R
0
-
12
R
0
-
11
R
0
-
10
R
0
-
R
9
0
-
R
8
0
-
R
7
0
-
R
6
0
-
R
5
0
-
TSR4
R
4
0
TSR3
R
3
0
TSR2
R
2
0
TSR1
R
1
0
TSR0
R
0
0