R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 294

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
• CS4WCR
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 262 of 1650
REJ09B0313-0300
Bit
31 to 21
20
19
18 to 16
R/W:
R/W:
Bit:
Bit:
31
15
R
R
0
0
Bit Name
⎯
BAS
⎯
WW[2:0]
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
0
0
000
R/W
28
12
R
0
0
-
SW[1:0]
R/W
27
11
R
0
0
-
R/W
R
R/W
R
R/W
R/W
26
10
R
0
1
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read access cycle
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
R/W
25
R
0
9
0
-
WR[3:0]
asserts the RD/WR signal during the write access
cycle.
and asserts the RD/WR signal at the write timing.
read access wait cycles)
R/W
24
R
0
8
1
-
R/W
23
R
0
7
0
-
R/W
WM
22
R
0
6
0
-
21
R
R
0
5
0
-
-
R/W
BAS
20
R
0
4
0
-
19
R
R
0
3
0
-
-
R/W
18
R
0
2
0
-
WW[2:0]
R/W
R/W
17
0
1
0
HW[1:0]
R/W
R/W
16
0
0
0