R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 815

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

In serial reception, the SCIF operates as described below.

1. The SCIF synchronizes with serial clock input or output and starts the reception.

2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the

3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in

Figure 15.17 shows an example of SCIF receive operation.

Serial clock

data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this

check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If

the check is not passed (overrun error is detected), further reception is prevented.

SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and

the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE)

in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).

Figure 15.17 Example of SCIF Receive Operation

Data read from SCFRDR and

RDF flag cleared to 0 by RXI

interrupt handler

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Sep. 28, 2009 Page 783 of 1650

BRI interrupt request

by overrun error

REJ09B0313-0300