R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 446

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 10 Direct Memory Access Controller (DMAC)
10.3.8
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
priority level of channels at the DMA transfer. This register also shows the DMA transfer status.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 414 of 1650
REJ09B0313-0300
Bit
15, 14
13, 12
11, 10
Note:
R/W:
Bit:
*
DMA Operation Register (DMAOR)
Only 0 can be written to clear the flag after 1 is read.
Bit Name
⎯
CMS[1:0]
⎯
15
R
0
-
14
R
0
-
R/W
13
0
CMS[1:0]
Initial
Value
All 0
00
All 0
R/W
12
0
11
R
0
-
R/W
R
R/W
R
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cycle Steal Mode Select
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
9
0
PR[1:0]
Executes one DMA transfer for every 16 cycles of
Bφ clock.
Executes one DMA transfer for every 64 cycles of
Bφ clock.
R/W
8
0
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
R/(W)* R/(W)* R/W
AE
2
0
NMIF
1
0
DME
0
0