R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1674

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Cache operations..................................... 232
Calculating exception handling vector
table addresses ........................................ 128
CAN bus interface ................................ 1015
CAN interface......................................... 918
Canceling software standby mode
(WDT) .................................................... 684
Cascaded operation................................. 535
Caution on period setting........................ 615
Changing the division ratio..................... 117
Changing the frequency.................. 116, 684
Changing the multiplication rate ............ 116
Clock frequency control circuit .............. 107
Clock operating modes ........................... 109
Clock pulse generator (CPG).................. 105
Clock timing ......................................... 1532
Clocked synchronous serial format......... 861
CMCNT count timing............................. 669
Coherency of cache and external
memory................................................... 233
Color-palette data format...................... 1277
Command access mode ........................ 1085
Compare match timer (CMT) ................. 663
Complementary PWM mode .................. 555
Conditions for determining number of
idle cycles ............................................... 381
Conditions for generating a
transaction............................................. 1228
Configuration of RCAN-TL1 ................. 990
Conflict between byte-write and
count-up processes of CMCNT .............. 674
Conflict between word-write and
count-up processes of CMCNT .............. 673
Conflict between write and
compare-match processes of CMCNT.... 672
Conflict error .......................................... 822
Control signal timing ............................ 1536
Control transfer stage transition
interrupt ................................................ 1186
Rev. 3.00 Sep. 28, 2009 Page 1642 of 1650
REJ09B0313-0300
Control transfers when the function
controller function is selected ............... 1214
Control transfers when the host
controller function is selected ............... 1213
Controller area network (RCAN-TL1).... 913
CPU........................................................... 47
Crystal oscillator ..................................... 107
CSn assert period expansion ................... 311
Cycle steal mode..................................... 435
D
D/A converter (DAC) ........................... 1045
D/A converter characteristics................ 1605
D/A output hold function in
software standby mode ......................... 1051
Data array........................................ 220, 235
Data array read........................................ 235
Data array write ...................................... 236
Data format in registers............................. 52
Data formats in memory ........................... 52
Data PID sequence bit........................... 1195
Data transfer instructions .......................... 73
Data transfer with interrupt request
signals ..................................................... 193
DC characteristics ................................. 1523
Deep power-down mode ......................... 359
Deep standby mode............................... 1428
Definitions of A/D conversion
accuracy ................................................ 1040
Delayed branch instructions...................... 55
Denormalized numbers ............................. 98
Device state transition interrupt ............ 1184
Direct memory access controller
(DMAC).................................................. 393
Displacement accessing ............................ 57
Divider 1 ................................................. 107
Divider 2 ................................................. 107
DMA transfer flowchart.......................... 422
DMAC activation.................................... 601
DMAC interface ................................... 1014