R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 811

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Figure 15.12 shows a sample flowchart for initializing the SCIF.
PFC setting for external pins used
Set RTRG[1:0] and TTRG[1:0] bits
Set TE and RE bits in SCSCR
Set TFRST and RFRST bits
in SCFCR, and clear TFRST
Figure 15.12 Sample Flowchart for SCIF Initialization
and BRK flags in SCFSR,
and RE bits cleared to 0)
Set data transfer format
Set CKE[1:0] in SCSCR
in SCFCR to 1 to clear
to 1, and set TIE, RIE,
After reading ER, DR,
Clear TE and RE bits
(leaving TIE, RIE, TE,
write 0 to clear them
Set value in SCBRR
Start of initialization
and RFRST bits to 0
End of initialization
the FIFO buffer
SCK, TxD, RxD
in SCSCR to 0
and REIE bits
in SCSMR
Section 15 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
Set the data transfer format in
SCSMR.
Set CKE[1:0].
Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used.
Sets PFC for external pins used.
Set as RxD input at receiving and
TxD at transmission.
Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the TxD,
RxD, and SCK pins to be used.
When transmitting, the TxD pin
will go to the mark state.
When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCK pin at this
point.
Rev. 3.00 Sep. 28, 2009 Page 779 of 1650
REJ09B0313-0300