R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 404

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
(2)
Basic Timing for I/O Card Interface
Figures 9.45 and 9.46 show the basic timing for the PCMCIA I/O card interface.
When accessing an I/O card through the PCMCIA interface, be sure to access the space as cache-
disabled.
Switching between I/O card and IC memory card interfaces in the respective address spaces is
accomplished by the SA[1:0] bit settings in CS5WCR and CS6WCR.
The IOIS16 pin can be used for dynamic adjustment of the width of the I/O bus in access to an I/O
card via the PCMCIA interface when little endian mode has been selected. When the bus width of
area 5 or 6 is set to 16 bits and the IOIS16 signal is driven high during a cycle of word-unit access
to the I/O card bus, the bus width will be recognized as 8 bits and only 8 bits of data will be
accessed during the current cycle of the I/O card bus. Operation will automatically continue with
access to the remaining 8 bits of data.
The IOIS16 signal is sampled on falling edges of the CKIO in Tpci0 as well as all Tpci0w cycles
for which the TED3 to TED0 bits are set to 1.5 cycles or more, and the CE2A and CE2B signals
are updated after 1.5 cycles of the CKIO signal from the sampling point of Tpci0. Ensure that the
IOIS16 signal is defined at all sampling points and does not change along the way.
Set the TED3 to TED0 bits to satisfy the requirement of the PC card in use with regard to setup
timing from ICIORD or ICIOWR to CE1 or CE2.
The basic waveforms for dynamic bus-size adjustment are shown in figure 9.46.
Since the IOIS16 signal is not supported in big endian mode, the IOIS16 signal should be fixed to
the low level when big endian mode has been selected.
Rev. 3.00 Sep. 28, 2009 Page 372 of 1650
REJ09B0313-0300