R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1143

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

23.3.4
TESTMODE is a register that controls the USB test signal output and the module’s internal USB
transceiver during high-speed operation. This register is initialized by a power-on reset. A
software reset initializes the UTST bits.
Initial value:
Bit
15
14 to 9
8
7 to 4
R/W:
Bit:
HOST
R/W
PCC
Test Mode Register (TESTMODE)
Bit Name
HOSTPCC
⎯
⎯
⎯
15
0
14
R
0
-
13
R
0
-
Initial
Value
0
All 0
1
All 0
12
R
0
-
11
R
0
-
R/W
R/W
R
R
R
10
R
0
-
R
9
0
-
Description
Disconnect Detector Power Switching
Sets the USB transceiver*.
This bit can only be set if the UACKEY0 and
UACKEY1 bits in the device control register have
been set.
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
The value of this bit when read depends on the
values of the UACKEY0 and UACKEY1 bits. When
UACKEY0 and UACKEY1 are both cleared to 0, it is
always read as 1, and writing to this bit has no effect.
When UACKEY0 is cleared to 0 and UACKEY1 is set
to 1, it is always read as 0. In this case, the write
value should also always be 0.*
Reserved
These bits are always read as 0. The write value
should always be 0.
R
8
1
-
Section 23 USB 2.0 Host/Function Module (USB)
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1111 of 1650
R
6
0
-
R
5
0
-
R
4
0
-
R/W
3
0
REJ09B0313-0300
R/W
UTST[3:0]
2
0
R/W
1
0
R/W
0
0