R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 840

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 16 Synchronous Serial Communication Unit (SSU)

A transfer clock can be selected from among seven internal clocks and an external clock. Before

using this module, enable the SSCK pin function in the PFC. When the MSS bit in SSCRH is 1, an

internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the

clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin.

When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.

The relationship of clock phase, polarity, and transfer data depends on the combination of the

CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0. Figure 16.2

shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting

is valid. When SSUMS = 1, the transmit data change timing and receive data fetch timing are the

same as that shown as “(1) When CPHS = 0” in figure 16.2.

Setting the MLS bit in SSMR selects either MSB first or LSB first communication. When MLS =

0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB

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REJ09B0313-0300

(1) When CPHS = 0

(2) When CPHS = 1

Transfer Clock

Relationship of Clock Phase, Polarity, and Data

Figure 16.2 Relationship of Clock Phase, Polarity, and Data