R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 169

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

5.5.2
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts processing
according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels
of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely
using the interrupt priority registers 01, 02, and 05 to 17 (IPR01, IPR02, and IPR05 to IPR17) of
the INTC as shown in table 5.9. The priority levels that can be set are 0 to 15. Level 16 cannot be
set. See section 6.3.1, Interrupt Priority Registers 01, 02, 05 to 17 (IPR01, IPR02, IPR05 to
IPR17), for details of IPR01, IPR02, and IPR05 to IPR17.
Table 5.9
Type
NMI
User break
H-UDI
IRQ
PINT
On-chip peripheral module
Interrupt Priority Level
Interrupt Priority Order
Priority Level
16
15
15
0 to 15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level.
Fixed priority level.
Set with interrupt priority registers 01, 02, and 05
to 17 (IPR01, IPR02, and IPR05 to IPR17).
Rev. 3.00 Sep. 28, 2009 Page 137 of 1650
Section 5 Exception Handling
REJ09B0313-0300