R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 21

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

14.5 Usage Notes ....................................................................................................................... 718
Section 15 Serial Communication Interface with FIFO (SCIF) ........................721
15.1 Features ............................................................................................................................ 721
15.2 Input/Output Pins ............................................................................................................... 724
15.3 Register Descriptions ......................................................................................................... 725
15.4 Operation ........................................................................................................................... 763
15.5 SCIF Interrupts................................................................................................................... 785
15.6 Usage Notes ....................................................................................................................... 786
Section 16 Synchronous Serial Communication Unit (SSU) ............................791
16.1 Features ............................................................................................................................ 791
16.2 Input/Output Pins ............................................................................................................... 793
14.5.1
14.5.2
14.5.3
14.5.4
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.3.6
15.3.7
15.3.8
15.3.9
15.3.10 FIFO Data Count Set Register (SCFDR) ............................................................ 757
15.3.11 Serial Port Register (SCSPTR) ........................................................................... 758
15.3.12 Line Status Register (SCLSR) ............................................................................ 761
15.3.13 Serial Extension Mode Register (SCEMR)......................................................... 762
15.4.1
15.4.2
15.4.3
15.6.1
15.6.2
15.6.3
15.6.4
15.6.5
15.6.6
15.6.7
Register Writing during RTC Count................................................................... 718
Use of Real-time Clock (RTC) Periodic Interrupts............................................. 718
Transition to Standby Mode after Setting Register ............................................. 718
Notes on Register Read and Write Operations.................................................... 719
Receive Shift Register (SCRSR)......................................................................... 727
Receive FIFO Data Register (SCFRDR) ............................................................ 727
Transmit Shift Register (SCTSR) ....................................................................... 728
Transmit FIFO Data Register (SCFTDR) ........................................................... 728
Serial Mode Register (SCSMR).......................................................................... 729
Serial Control Register (SCSCR)........................................................................ 732
Serial Status Register (SCFSR)........................................................................... 736
Bit Rate Register (SCBRR) ................................................................................ 744
FIFO Control Register (SCFCR) ........................................................................ 754
Overview............................................................................................................. 763
Operation in Asynchronous Mode ...................................................................... 766
Operation in Clock Synchronous Mode.............................................................. 777
SCFTDR Writing and TDFE Flag ...................................................................... 786
SCFRDR Reading and RDF Flag ....................................................................... 786
Restriction on DMAC Usage .............................................................................. 787
Break Detection and Processing ......................................................................... 787
Sending a Break Signal....................................................................................... 787
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .... 787
Selection of Base Clock in Asynchronous Mode................................................ 789
Rev. 3.00 Sep. 28, 2009 Page xix of xxx
REJ09B0313-0300