R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 157

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

5.1.2
The exception handling sources are detected and start processing according to the timing shown in
table 5.2.
Table 5.2
Exception
Reset
Address error
Interrupts
Register bank
error
Instructions
Exception Handling Operations
Timing of Exception Source Detection and Start of Exception Handling
Source
Power-on reset
Manual reset
Bank underflow
Bank overflow
Trap instruction
General illegal
instructions
Slot illegal
instructions
Integer division
exception
Starts when the MRES pin changes from low to high or when
Timing of Source Detection and Start of Handling
Starts when the RES pin changes from low to high, when the
H-UDI reset negate command is set after the H-UDI reset
assert command has been set, or when the WDT overflows.
the WDT overflows.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Starts upon attempted execution of a RESBANK instruction
when saving has not been performed to register banks.
In the state where saving has been performed to all register
bank areas, starts when acceptance of register bank overflow
exception has been set by the interrupt controller (the BOVE bit
in IBNR of the INTC is 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
Starts from the execution of a TRAPA instruction.
Starts from the decoding of undefined code anytime except
immediately after a delayed branch instruction (delay slot)
(including FPU instructions and FPU-related CPU instructions
in FPU module standby state).
Starts from the decoding of undefined code placed directly after
a delayed branch instruction (delay slot) (including FPU
instructions and FPU-related CPU instructions in FPU module
standby state), of instructions that rewrite the PC, of 32-bit
instructions, of the RESBANK instruction, of the DIVS
instruction, or of the DIVU instruction.
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by −1.
Rev. 3.00 Sep. 28, 2009 Page 125 of 1650
Section 5 Exception Handling
REJ09B0313-0300