R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1188

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
23.3.30 DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, change and confirm the
data PID sequence bit, and set the response PID for the DCP.
This register is initialized by a power-on reset or a software reset. The CCPL and PID[2:0] bits are
initialized by a USB bus reset.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1156 of 1650
REJ09B0313-0300
Bit
15
14
13 to 9
8
7
R/W:
Bit:
BSTS SUREQ
Bit Name
BSTS
SUREQ
⎯
SQCLR
SQSET
15
R
0
R/W*
14
0
2
13
R
0
-
12
Initial
Value
0
0
All 0
0
0
R
0
-
11
R
0
-
R/W
R
R/W*
R
R*
R*
10
R
0
-
1
1
/W*
/W*
2
2
2
R
9
0
-
Description
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled
The direction of buffer access, writing or reading,
depends on the ISEL bit in CFIFOSEL.
SETUP Token Transmission
Transmits the setup packet by setting this bit to 1.
This module clears this bit when the setup
transaction is completed. While this bit is 1,
USBREQ, USBVAL, USBINDX and USBLENG
should not be written to.
0: Invalid
1: Transmits the setup packet
Reserved
These bits are always read as 0. The write value
should always be 0.
Toggle Bit Clear*
0: Invalid
1: Specifies DATA0
Toggle Bit Set*
0: Invalid
1: Specifies DATA1
SQCLR SQSET SQMON
R*
W*
8
0
1
2
/
R*
W*
7
0
1
2
/
R
6
1
3
*
4
3
*
4
R
5
0
-
R
4
0
-
R
3
0
-
CCPL
R/W
2
0
R/W
1
0
PID[1:0]
R/W
0
0