R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1169

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Notes: 1. Only 0 can be written to.
23.3.17 Interrupt Status Register 1 (INTSTS1)
INTSTS1 is a register that is used to confirm interrupt status. The SOFR, BEMP, NRDY and
BRDY bits are mirror bits of INTSTS0. When these bits are read, the corresponding bit values in
INTSTS0 will be read. When these bits in INTSTS1 are written to, the written values are also
reflected in INTSTS0.
Interrupt generation can be confirmed simply by referencing one of the registers: INTSTS0 when
the peripheral controller function is selected and INTSTS1 when the host controller function is
selected.
This register is initialized by a power-on reset or a software reset.
Initial value:
Bit
2 to 0
R/W:
Bit:
2. If multiple sources have occurred among the VBINT, RESM, SOFR, DVST, and CTRT
3. This bit is initialized to 1 when the VBUS pin is high level and 0 when it is low level.
4. These bits are initialized to B'000 by a power-on reset or a software reset, and B'001 by
Bit Name
CTSQ[2:0]
15
R
0
-
bits, an access cycle of at least 140 ns and 3 bus clock cycles is required in order to
clear the bits in succession, not simultaneously.
a USB bus reset.
BCHG SOFR
R/W* R/W* R/W*
14
0
13
0
Initial
Value
000
DTCH
12
0
11
R
0
-
R/W
R
BEMP
10
R
0
NRDY
R
9
0
Description
Control Transfer Stage
000: Idle or setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (no data) status stage
110: Control transfer sequence error
111: Setting prohibited
BRDY
R
8
0
Section 23 USB 2.0 Host/Function Module (USB)
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1137 of 1650
R
6
0
-
SIGN
R/W*
5
0
SACK
R/W*
4
0
R
3
0
-
REJ09B0313-0300
R
2
0
-
R
1
0
-
R
0
0
-