R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 887

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

17.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
Note: If only one byte is received, read ICDRR (dummy-read) after the RCVD bit in ICCR1 is
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
This enables the issuance of the stop condition after the next reception.
set.
Master Receive Operation
Rev. 3.00 Sep. 28, 2009 Page 855 of 1650
Section 17 I
2
C Bus Interface 3 (IIC3)
REJ09B0313-0300