R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 944

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Section 18 Serial Sound Interface (SSI)

If an underflow or overflow occurs while the DMA is in operation, the module should be restarted.

The transmit and receive buffers in the SSI consists of 32-bit registers that share the L and R

channels. Therefore, data to be transmitted and received at the L channel may sometimes be

transmitted and received at the R channel if an underflow or overflow occurs, for example, under

the following condition: the control register (SSICR) has a 32-bit setting for both data word length

(DWL2 to DWL0) and system word length (SWL2 to SWL0).

If an error occurrence is confirmed with two types of error interrupts (underflow, overflow) or the

corresponding error status flag (the bits UIRQ, OIRQ in SSISR), write 0 to the EN and DMEN bit

in SSICR to disable DMA transfer requests in this module, thus stopping the operation. (In this

case, the direct memory access controller setting should also be stopped.) After this, write 0 to the

error status flag bit to clear the error status, set the direct memory access controller again and

restart the transfer.

Rev. 3.00 Sep. 28, 2009 Page 912 of 1650

REJ09B0313-0300

Limitations from Underflow or Overflow during DMA Operation