R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 835

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Bit
0
Bit Name
CE
Initial
Value
0
R/W
R/W
Description
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. In SSU mode, when
clearing RDRF in SSSR while reading receive data
(reading SSRDR) when a slave device is in the receive
operation state, or clearing TDRE in SSSR while writing
transmit data (writing to SSTDR) when a slave device is
in the transmit operation state, an incomplete error
occurs at the end of the frame, even if clearing does not
complete by the beginning of the next frame.
Data reception does not continue while the CE bit is set
to 1. Serial transmission also does not continue. Reset
the SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting conditions]
•
•
•
•
[Clearing condition]
•
Section 16 Synchronous Serial Communication Unit (SSU)
When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
At the end of the frame, when reading SSRDR and
clearing RDRF do not complete by the beginning of
the next frame during receive operation by a slave
device
At the end of the frame, when writing to SSTDR and
clearing TDRE do not complete by the beginning of
the next frame during transmit operation by a slave
device
When writing 0 after reading CE = 1
Rev. 3.00 Sep. 28, 2009 Page 803 of 1650
REJ09B0313-0300